DLPS096B November   2017  – May 2022 DLPC120-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 LED Driver Interface
    2. 5.2 DMD Temperature Interface
    3.     General Purpose I/O
    4. 5.3 Main Video and Data Control Interface
    5. 5.4 DMD Interface
    6. 5.5 Memory Interface
    7.     Board Level Test and Debug
    8.     Manufacturing Test Support
    9.     Test Point Interface
    10.     Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for I/O
    7. 6.7  Power Supply and Reset Timing Requirements
    8. 6.8  Reference Clock PLL Timing Requirements
    9. 6.9  Parallel Interface General Timing Requirements
    10. 6.10 Parallel Interface Frame Timing Requirements
    11. 6.11 Flash Memory Interface Timing Requirements
    12. 6.12 DMD Interface Timing Requirements
    13. 6.13 JTAG Interface Timing Requirements
    14. 6.14 I2C Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Parallel Interface Input Source Timing
    2. 7.2 Design for Test Functions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Flash Interface
      2. 8.3.2 Serial Flash Programming
      3. 8.3.3 DDR2 Memory Interface
      4. 8.3.4 JTAG and DMD Interface Test
      5. 8.3.5 Temperature Monitor Function
      6. 8.3.6 Host Command Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Video Mode
      2. 8.4.2 Splash Screen Mode
      3. 8.4.3 Test Pattern Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout guidelines for internal ASIC PLL power
      2. 11.1.2 DLPC120-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 PCB Routing Guidelines
      5. 11.1.5 Number of Layer Changes
      6. 11.1.6 Terminations
      7. 11.1.7 General Handling Guidelines for Unused CMOS-Type Pins
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
        1. 12.2.1.1 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZXS|216
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 LED Driver Interface

PIN I/O I/O CLOCK DESCRIPTION
NAME NO. POWER TYPE SYSTEM
LED_B_PWM D16 3.30 V O6 N/A Function reserved for future use.
LED_R_PWM (PWRGOOD_CNTRL) E14 O6 N/A Repurposed for power good control. Together with pin G13 (PWRGOOD), this signal is used for DLP30xx-Q1 parking as part of the preconditioning sequence and subsequent unparking. See the DLPC120-Q1 Programmer's Guide for implementation details.
LED_G_PWM F13 O6 N/A Function reserved for future use.
LED_B_EN C15 O6 N/A Blue LED enable strobe. Controlled by programmable DMD sequence timing (active high)
LED_R_EN C16 O6 N/A Red LED enable strobe. Controlled by programmable DMD sequence timing (active high)
LED_G_EN D14 O6 N/A Green LED enable strobe. Controlled by programmable DMD sequence timing (active high)
LED_S_EN B16 O6 N/A LED shunt enable. Controlled by programmable DMD sequence timing (active high)
LED_D_EN E13 O6 N/A LED drive enable. Controlled by programmable DMD sequence timing (active high)
LEDDRV_ON D15 O6 Async LED driver enable. Active high output control to external LED drive logic
LED_EN F16 I2 Async LED enable (active high input). A logic low on this signal forces LEDDRV_ON low and RGB strobes low. These signals are enabled 100 ms after LED_EN transitions to a high (assuming corresponding SW parameters are also set to enable LED operation).
LED_COMPZ D13 I2 Async LED threshold compare (active low input). A logic low on this signal indicates a threshold is reached, and in discontinuous mode controls shunt enable (LED_S_EN).
AST_CLR0 L12 O6 N/A Function reserved for future use
AST_HLD0 M13 O6 N/A Function reserved for future use
AST_INTR0 L13 O6 N/A Sequence timer interrupt port
AST_CLR1 M12 O6 N/A Function reserved for future use
AST_HLD1 R16 O6 N/A Function reserved for future use
AST_INTR1 M14 O6 N/A Function reserved for future use