DLPS096B November   2017  – May 2022 DLPC120-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 LED Driver Interface
    2. 5.2 DMD Temperature Interface
    3.     General Purpose I/O
    4. 5.3 Main Video and Data Control Interface
    5. 5.4 DMD Interface
    6. 5.5 Memory Interface
    7.     Board Level Test and Debug
    8.     Manufacturing Test Support
    9.     Test Point Interface
    10.     Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for I/O
    7. 6.7  Power Supply and Reset Timing Requirements
    8. 6.8  Reference Clock PLL Timing Requirements
    9. 6.9  Parallel Interface General Timing Requirements
    10. 6.10 Parallel Interface Frame Timing Requirements
    11. 6.11 Flash Memory Interface Timing Requirements
    12. 6.12 DMD Interface Timing Requirements
    13. 6.13 JTAG Interface Timing Requirements
    14. 6.14 I2C Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Parallel Interface Input Source Timing
    2. 7.2 Design for Test Functions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Flash Interface
      2. 8.3.2 Serial Flash Programming
      3. 8.3.3 DDR2 Memory Interface
      4. 8.3.4 JTAG and DMD Interface Test
      5. 8.3.5 Temperature Monitor Function
      6. 8.3.6 Host Command Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Video Mode
      2. 8.4.2 Splash Screen Mode
      3. 8.4.3 Test Pattern Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout guidelines for internal ASIC PLL power
      2. 11.1.2 DLPC120-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 PCB Routing Guidelines
      5. 11.1.5 Number of Layer Changes
      6. 11.1.6 Terminations
      7. 11.1.7 General Handling Guidelines for Unused CMOS-Type Pins
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
        1. 12.2.1.1 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZXS|216
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Power Supply and Reset Timing Requirements

MINMAXUNIT
trampTime for all DLPC120-Q1 power rails to be appliedPower supplies can be applied in any order if they occur within this maximum timing. Otherwise, refer to Note (1).10ms
tpwr_enRESETZ rising edge (or PWRGOOD rising edge—whichever comes second) to DMD_PWR_EN rising edgePWRGOOD shall be controlled by LED_R_PWM / PWRGOOD_CNTRL signal, which is an output of the DLPC120-Q1 and will automatically be asserted after the device releases from reset.150µs
tdlyExternal delay between DMD_PWR_EN and DMD mirror supply voltages

This delay is not required for supported devices.

ms
toezDMD_PWR_EN rising edge to falling edge of DMD_OEZ5ms
tpreconditionDMD preconditioning timeIIt is required that the DMD executes a Pre-Conditioning Sequence prior to parking. The final action of this sequence is the de-assertion of the LED_R_PWM / PWRGOOD_CNTRL signal, which shall drive the PWRGOOD signal low. See the DLPC120-Q1 Programmer's Guide for instructions on how to execute the Pre-Conditioning Sequence.800µs
tparkDMD park time (approximate)200200µs
tpd_dmdPWRGOOD low to falling edge of DMD_PWR_EN500µs
tfallTime for DLPC120-Q1 power supplies to be removedPower supplies can be removed in any order if they occur within this maximum timing. Otherwise, they shall be removed in the reverse order they were applied, per the tramp specification and Note (1).10ms
(1) If the DLPC120-Q1 supplies cannot be applied according to this timing specification, then they must be applied in the following order, spanning no longer than 100 ms (shall be removed in the reverse order for power down):
  1. Apply VCCIO_2 (3.3 V)
  2. Apply VCCIO_0, VCCIO_1 (1.8 V) DDR Memory and DMD, in any order
  3. Apply VDD (1.2 V) DLPC120-Q1 core supply voltage
GUID-9503794E-7C51-4B6F-94FF-B634D6B2ECDC-low.gifFigure 6-1 Power Supply and RESETZ Timing