DLPS014F April   2010  – May 2018 DLPC200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2.     Power and Ground Pins
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  I/O Electrical Characteristics
    6. 6.6  Video Input Pixel Interface Timing Requirements
    7. 6.7  I2C Interface Timing Requirements
    8. 6.8  USB Read Interface Timing Requirements
    9. 6.9  USB Write Interface Timing Requirements
    10. 6.10 SPI Slave Interface Timing Requirements
    11. 6.11 Parallel Flash Interface Timing Requirements
    12. 6.12 Serial Flash Interface Timing Requirements
    13. 6.13 Static RAM Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 DLPA200 Interface Timing Requirements
    16. 6.16 DDR2 SDR Memory Interface Timing Requirements
    17. 6.17 Video Input Pixel Interface – Image Sync and Blanking Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Frame Rates
    4. 7.4 Device Functional Modes
      1. 7.4.1 Video Modes
      2. 7.4.2 Structured Light Modes
        1. 7.4.2.1 Static Image Buffer Mode
        2. 7.4.2.2 Real Time Structured Light Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DLPC200 System Interfaces
          1. 8.2.2.1.1  DLPC200 Master, I2C Interface for EDID Programming
          2. 8.2.2.1.2  USB Interface
          3. 8.2.2.1.3  Bus Protocol
          4. 8.2.2.1.4  SPI Slave Interface
          5. 8.2.2.1.5  Parallel Flash Memory Interface
          6. 8.2.2.1.6  Serial Flash Memory Interface
          7. 8.2.2.1.7  SRAM Interface
          8. 8.2.2.1.8  DDR2 SDR Memory Interface
          9. 8.2.2.1.9  Projector Image and Control Port Signals
          10. 8.2.2.1.10 SDRAM Memory
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements
    2. 9.2 Power-Down Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Impedance Requirements
      2. 10.1.2 PCB Signal Routing
      3. 10.1.3 Fiducials
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Heat Sink
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Marking
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.1.9 Projector Image and Control Port Signals

The DLPC200 provides two input ports for graphics and motion video inputs. The following listed signals support the two input interface modes.

Following are the two input image interface modes, signal descriptions, and pins needed on the DLPC200.

  • PORT 1, 28 pins (HDMI connector)
    • PORT1_D(23-0) – Projector data
    • PORT1_VSYNC – Vertical sync
    • PORT1_HSYNC – Horizontal sync
    • PORT1_IVALID – Data enable
    • PORT1_CLK – Projector clock (rising edge or falling edge, to capture input data)
  • PORT 2, 28 pins (expansion connector)
    • PORT2_D(23-0) – Projector data
    • PORT2_VSYNC – Vertical sync
    • PORT2_HSYNC – Horizontal sync
    • PORT2_IVALID – Data enable
    • PORT2_CLK – Projector clock (rising edge or falling edge, to capture input data)

Two control interfaces, USB and SPI, are provided to configure the DLPC200, as well as to transmit pattern data to memory for structured light mode. Following are the pins needed for the SPI and USB control interfaces.

  • USB, 48 MHz
    • USB_CLK – USB clock
    • USB_CTRL1 – FIFO full flag
    • USB_CTRL2 – FIFO empty flag
    • USB_FD(15–0) – USB data
    • USB_PA02 – FIFO output enable for reads
    • USB_PA04 – FIFO address bit
    • USB_PA05 – FIFO address bit
    • USB_RDY1 – Write enable
    • USB_RDY0 – Read enable
  • SPI, 5 MHz
    • SLAVE_SPI_CLK – SPI clock
    • SLAVE_SPI_ACK – Busy signal that holds off additional transactions until the slave has completed processing data
    • SLAVE_SPI_MISO – Output from slave
    • SLAVE_SPI_MOSI – Output from master
    • SLAVE_SPI_CS – Slave select

Images are displayed via control of the DMD and DLPA200. The DLPC200 DMD interface consists of a 200-MHz (nominal) half-bus DDR output-only interface with LVDS signaling. The serial communications port (SCP), 125-kHz nominal, is used to read or write control data to both the DMD and the DLPA200. The following listed signals support data transfer to the DMD and DLPA200.

  • DMD, 200 MHz
    • DMD_CLK_AP, DMD_CLK_AN – DMD clock for A
    • DMD_CLK_BP, DMD_CLK_BN – DMD clock for B
    • DMD_DAT_AP, DMD_DAT_AN(1, 3, 5, 7, 9, 11, 13, 15) – Data bus A (odd-numbered pins are used for half-bus)
    • DMD_DAT_BP, DMD_DAT_BN(1, 3, 5, 7, 9, 11, 13, 15) – Data bus B (odd-numbered pins are used for half-bus)
    • DMD_SCRTL_AP, DMD_SCRTL_AN – S-control for A
    • DMD_SCRTL_BP, DMD_SCRTL_BN – S-control for B
  • DLPA200, 125 kHz
    • SCP_DMD_RST_CLK – SCP clock
    • SCP_DMD_EN – Enable DMD communication
    • SCP_RST_EN – Enable DLPA200 communication
    • SCP_DMD_RST_DI – Input data
    • SCP_DMD_RST_DO – Output data