DLPS014F April   2010  – May 2018 DLPC200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2.     Power and Ground Pins
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  I/O Electrical Characteristics
    6. 6.6  Video Input Pixel Interface Timing Requirements
    7. 6.7  I2C Interface Timing Requirements
    8. 6.8  USB Read Interface Timing Requirements
    9. 6.9  USB Write Interface Timing Requirements
    10. 6.10 SPI Slave Interface Timing Requirements
    11. 6.11 Parallel Flash Interface Timing Requirements
    12. 6.12 Serial Flash Interface Timing Requirements
    13. 6.13 Static RAM Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 DLPA200 Interface Timing Requirements
    16. 6.16 DDR2 SDR Memory Interface Timing Requirements
    17. 6.17 Video Input Pixel Interface – Image Sync and Blanking Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Frame Rates
    4. 7.4 Device Functional Modes
      1. 7.4.1 Video Modes
      2. 7.4.2 Structured Light Modes
        1. 7.4.2.1 Static Image Buffer Mode
        2. 7.4.2.2 Real Time Structured Light Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DLPC200 System Interfaces
          1. 8.2.2.1.1  DLPC200 Master, I2C Interface for EDID Programming
          2. 8.2.2.1.2  USB Interface
          3. 8.2.2.1.3  Bus Protocol
          4. 8.2.2.1.4  SPI Slave Interface
          5. 8.2.2.1.5  Parallel Flash Memory Interface
          6. 8.2.2.1.6  Serial Flash Memory Interface
          7. 8.2.2.1.7  SRAM Interface
          8. 8.2.2.1.8  DDR2 SDR Memory Interface
          9. 8.2.2.1.9  Projector Image and Control Port Signals
          10. 8.2.2.1.10 SDRAM Memory
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements
    2. 9.2 Power-Down Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Impedance Requirements
      2. 10.1.2 PCB Signal Routing
      3. 10.1.3 Fiducials
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Heat Sink
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Marking
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Video Input Pixel Interface Timing Requirements

PARAMETER TEST CONDITIONS MIN MAX UNIT
ƒpclock Clock frequency, PORTx_CLK 80 MHz
tp_wh Pulse duration, high 45% to 55% reference points (signal) 5.6 ns
tp_wl Pulse duration, low 45% to 55% reference points (signal) 5.6 ns
tp_su Setup time, PORTx_D(23–0) valid before PORTx_CLK See (1) 1.5 ns
tp_h Hold time, PORTx_D(23–0) valid after PORTx_CLK See (1) 1.5 ns
tp_su Setup time, PORTx_VSYNC valid before PORTx_CLK See (1) 1.5 ns
tp_h Hold time, PORTx_VSYNC valid after PORTx_CLK See (1) 1.5 ns
tp_su Setup time, PORTx_HSYNC valid before PORTx_CLK See (1) 1.5 ns
tp_h Hold time, PORTx_HSYNC valid after PORTx_CLK See (1) 1.5 ns
tp_su Setup time, PORTx_IVALID valid before PORTx_CLK See (1) 1.5 ns
tp_h Hold time, PORTx_IVALID valid after PORTx_CLK See (1) 1.5 ns
(1) PCLK may be inverted from that shown in Figure 1. In that case, the same specifications in the table are valid except now referenced to the falling edge of the clock. If the falling edge of PCLK is used, a USB or SPI command must be sent to tell the DLPC200 to use the falling edge of PCLK.
DLPC200 port2inputint_lps014.gifFigure 1. Input Port Interface

See Pin Configuration and Functions for the proper connection schema if a video input port will not be used.