DLPS054I December 2015 – August 2024 DLPC230-Q1 , DLPC231-Q1
PRODUCTION DATA
(1) | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
fclock | Clock frequency, FLSH_SPI_CLK | When VCC3IO_FLSH = 3.3VDC | 9.998 | 50.01(2) | MHz |
tp_clkper | Clock period, FLSH_SPI_CLK (50% reference points) | When VCC3IO_FLSH = 3.3VDC | 20.0 | 100 | ns |
tp_wh | Pulse duration low, FLSH_SPI_CLK (50% reference points) | When VCC3IO_FLSH = 3.3VDC | 9 | ns | |
tp_wl | Pulse duration high, FLSH_SPI_CLK (50% reference points) | When VCC3IO_FLSH = 3.3VDC | 9 | ns | |
tt | Transition time – all input signals | 20% to 80% reference points | 6 | ns | |
tp_su | Setup time – FLSH_SPI_DIO[3:0] valid before FLSH_SPI_CLK falling edge (50% reference points) | When VCC3IO_FLSH = 3.3VDC | 7.0 | ns | |
tp_h | Hold time – FLSH_SPI_DIO[3:0] valid after FLSH_SPI_CLK falling edge | 50% reference points | 0.0 | ns | |
tp_clqv | FLSH_SPI_DIO[3:0] output delay valid time (with respect to falling edge of FLSH_SPI_CLK or falling edge of FLSH_SPI_CSZ) | When VCC3IO_FLSH = 3.3VDC | –3.0 | 3.0 | ns |