DLPS201E August   2020  – August 2024 DLPC230S-Q1 , DLPC231S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics for Fixed Voltage I/O
    7. 5.7  DMD High-Speed SubLVDS Electrical Characteristics
    8. 5.8  DMD Low-Speed SubLVDS Electrical Characteristics
    9. 5.9  OpenLDI LVDS Electrical Characteristics
    10. 5.10 Power Dissipation Characterisics
    11. 5.11 System Oscillators Timing Requirements
    12. 5.12 Power Supply and Reset Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 OpenLDI Interface General Timing Requirements
    15. 5.15 Parallel/OpenLDI Interface Frame Timing Requirements
    16. 5.16 Host/Diagnostic Port SPI Interface Timing Requirements
    17. 5.17 Host/Diagnostic Port I2C Interface Timing Requirements
    18. 5.18 Flash Interface Timing Requirements
    19. 5.19 TPS99000S-Q1 SPI Interface Timing Requirements
    20. 5.20 TPS99000S-Q1 AD3 Interface Timing Requirements
    21. 5.21 DLPC23xS-Q1 I2C Port Interface Timing Requirements
    22. 5.22 Chipset Component Usage Specification
  7. 6 Parameter Measurement Information
    1. 6.1 HOST_IRQ Usage Model
    2. 6.2 Input Source
      1. 6.2.1 Supported Input Sources
      2. 6.2.2 Parallel Interface Supported Data Transfer Formats
        1. 6.2.2.1 OpenLDI Interface Supported Data Transfer Formats
          1. 6.2.2.1.1 OpenLDI Interface Bit Mapping Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Parallel Interface
      2. 7.3.2  OpenLDI Interface
      3. 7.3.3  DMD (SubLVDS) Interface
      4. 7.3.4  Serial Flash Interface
      5. 7.3.5  Serial Flash Programming
      6. 7.3.6  Host Command and Diagnostic Processor Interfaces
      7. 7.3.7  GPIO Supported Functionality
      8. 7.3.8  Built-In Self Test (BIST)
      9. 7.3.9  EEPROMs
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Debug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Display Mode
      3. 7.4.3 Calibration Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Head-Up Display
        1. 8.2.1.1 Design Requirements
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Management
      2. 8.3.2 Hot Plug Usage
      3. 8.3.3 Power Supply Filtering
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
        2. 8.4.1.2  DLPC23xS-Q1 Reference Clock
          1. 8.4.1.2.1 Recommended Crystal Oscillator Configuration
        3. 8.4.1.3  DMD Interface Layout Considerations
        4. 8.4.1.4  General PCB Recommendations
        5. 8.4.1.5  General Handling Guidelines for Unused CMOS-Type Pins
        6. 8.4.1.6  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
        7. 8.4.1.7  Number of Layer Changes
        8. 8.4.1.8  Stubs
        9. 8.4.1.9  Terminations
        10. 8.4.1.10 Routing Vias
      2. 8.4.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Device Nomenclature
        1. 9.1.2.1 Device Markings DLPC230-Q1 or DLPC230S-Q1
        2. 9.1.2.2 Device Markings DLPC231-Q1 or DLPC231S-Q1
        3. 9.1.2.3 Video Timing Parameter Definitions
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZDQ|324
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 Serial Flash Interface

The DLPC23xS-Q1 uses an external SPI serial flash memory device for configuration and operational data. The minimum supported size is 16 Mb. Larger devices can be required based on operation data and splash image size. The maximum supported size is 128 Mb. It must be noted that the system will support 256 Mb and 512 Mb devices, however, only the first 128 Mb of space are used.

The external serial flash device is supported on a single SPI interface and mostly complies with industry standard SPI flash protocol (See Figure 5-8). The Host will specify the maximum supported flash interface frequency (which can be based on device limits, system limits, and/or other factors) and the system will program the closest obtainable value less than or equal to this specified maximum.

The DLPC23xS-Q1 ASIC flash must be connected to the designated SPI flash interface (FLSH_SPI_xxx) to enable support for system initialization, configuration, and operation.

The DLPC23xS-Q1 must support any flash device that is compatible with the modes of operation, features, and performance as defined in this section.

Table 7-2 SPI Flash Required Features or Modes of Operation
FEATUREDLPC23xS-Q1 REQUIREMENTCOMMENTS
SPI interface widthSingle Wire, Two Wire, Four Wire
SPI protocolSPI mode 0
Fast READ addressingAuto-incrementing
Programming modePage mode
Page size256 Bytes
Sector (or Subsector) size4 KBRequired erase granularity
Block structureUniform sector / Subsector
Block protection bits0 = Disabled (with Default = 0 = Disabled)
Status register bit(0)Write in progress (WIP) {also called flash busy}
Status register bit(1)Write enable latch (WEN)
Status register bits(6:2)A value of 0 disables programming protection
Status register bit(7)Status register write protect (SRWP)
Status register bits(15:8) (expanded status register), or
Secondary Status register		The DLPC23xS-Q1 supports multi-byte status registers, as well as separate, additional status registers, but only for specific devices/register addresses. The supported registers and addresses are specified in Table 7-3.
CAUTION:

The selected SPI flash device must block repeated status writes from being written to internal register. The boot application writes to the flash device status register once per 256 bytes during programming. Most flash devices discard status register writes when the status content does not change. Some flash parts, such as the Micron N25Q128A13ESFA0F, do not block status writes when the status data is repeated. This causes the status register to exceed its maximum write limit after several programming cycles, making them incompatible with the DLPC23xS-Q1. Note that the main application does not write to the status register.

For each write operation, the DLPC23xS-Q1 boot application executes the following:

  1. Write enable command
  2. Write status command (to unprotect memory)
  3. Read status command to poll the successful execution of the write status (repeated as needed)
  4. Write enable command
  5. Program or erase command
  6. Read status command (repeated as needed) to poll the successful execution of the program or erase operation
  7. Write disable command (during programming; this is not performed after erase command)

For each write operation, the DLPC23xS-Q1 main application executes the following:

  1. Write enable command
  2. Program or erase command
  3. Read status command (repeated as needed) to poll the successful execution of the program or erase operation
  4. Write disable command (during programming; this is not performed after erase command)

The specific instruction op-code and timing compatibility requirements are listed in Table 7-3 and Flash Interface Timing Requirements. Note that DLPC23xS-Q1 does not read the flash’s full electronic signature ID and thus cannot automatically adapt protocol and clock rates based on the ID.

Table 7-3 SPI Flash Instruction Op-Code and Access Profile Compatibility Requirements
SPI FLASH
COMMAND		FIRST BYTE
(OP-CODE)		SECOND BYTETHIRD BYTEFOURTH BYTEFIFTH BYTESIXTH BYTENO. OF DUMMY CLOCKSCOMMENTS
Fast READ (1/1)0x0BADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)(1)8See Table 7-4.
Dual READ (1/2)0x3BADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)(1)8See Table 7-4.
2X READ (2/2)0xBBADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)(1)4See Table 7-4.
Quad READ (1/4)0x6BADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)(1)8See Table 7-4.
4X READ (4/4)0xEBADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)(1)6See Table 7-4.
Read status0x05n/an/aSTATUS(0)STATUS(1)0Status(1) - Winbond only
Write status0x01STATUS(0)STATUS(1)0Status(1) - Winbond only
Read Volatile
Conf Reg		0x85Data(0)0Micron Only
Write Volatile
Conf Reg		0x81Data(0)0Micron Only
Write Enable0x060
Write Disable0x040
Page program0x02ADDRS(0)ADDRS(1)ADDRS(2)DATA(0)(1)0
Sector/Subsector
Erase (4KB)		0x20ADDRS(0)ADDRS(1)ADDRS(2)0
Full Chip Erase0xC70
Software Reset
Enable		0x66
Software Reset0x99
Read Id0x9FData(0)Data(1)Data(2)System only reads 1st three bytes.
(1) Only the first data byte is shown, data continues.

More detailed information on the various read operations supported are shown in Table 7-4.

Table 7-4 SPI Flash Supported Read Operation Details
READ TYPE(2)NUMBER OF LINES FOR OP-CODE(1)NUMBER OF LINES FOR ADDRESSNUMBER OF LINES FOR DUMMY BYTESNUMBER OF LINES FOR RETURN DATA
Fast Read (1/1)1111
Dual Read (1/2)1112
2X Read (2/2)1222
Quad Read (1/4)1114
4X Read (4/4)1444
(1) System does not support Read op-codes being spread across more than one data line.
(2) Flash vendors have diverged in naming and controlling their various read capabilities. As such, the Host needs to be very careful to fully understand what is and what is not supported by the DLPC23xS-Q1. In general, for the supported devices, the DLPC23xS-Q1 only supports "Extended SPI" or "SPI Mode" (as defined in the various Flash Data Sheets). It does not support "Dual SPI Mode", "Quad SPI Mode", "QPI", "QPI Mode", "Dual QPI", "Quad QPI", "DTR", or "DDR". If uncertain, most devices will support "Fast Reads" in a manner that is consistent with the DLPC23xS-Q1.
Table 7-5 DLPC23xS-Q1 Compatible SPI Flash Device Options
DENSITY (M-BITS) (2)(3)VENDORPART NUMBERPACKAGE SIZE
3.3V Compatible Devices
128Micron(1)MT25QL128ABA8ESF-OAATSO16
128MacronixMX25L12835FMR-10GSO16
128MacronixMX25L12845GMR-10GSO16
128MacronixMX25L12839FXDQ-10GBGA25
(1) Care must be used when considering Numonyx versions of Micron serial flash devices as they typically do not have the 4KB sector size needed to be DLPC23xS-Q1 compatible.
(2) For any devices not listed on this table, special care must be taken to insure that the requirements shown in Table 7-2 and Table 7-3 are met.
(3) The boot application writes to the flash device status register once per 256 bytes during programming. Most flash devices discard status register writes when the status content does not change. Some flash parts, such as Micron N25Q128A13ESFA0F, do not block status writes when the status data is repeated. This causes the status register to exceed its maximum write limit after several programming cycles, making them incompatible with the DLPC23xS-Q1. Note that the main application does not write to the status register.

While the DLPC23xS-Q1 supports a variety of clock rates and read operation types, it does have a minimum flash read bandwidth requirement which is shown in Table 7-6. This minimum read bandwidth can be met in any number of different ways, with the variables being clock rate and read type. The Host is required to select a flash device which can meet this minimum read bandwidth using the DLPC23xS-Q1 supported interface capabilities. It must be noted that the Host will specify to the system (through flash parameter) the maximum supported clock rate as well as the supported read types for their selected flash device, with which the DLPC23xS-Q1 SW will automatically select an appropriate combination to maximize this bandwidth (which must at least meet the minimum bandwidth requirement assuming a solution exists per the specified parameters).

Table 7-6 SPI Flash Interface Bandwidth Requirements
PARAMETERMINMAXUNIT
FLSH_RDBWFlash Read Interface Bandwidth47.00Mbps