DLPS030E December   2013  – March 2019 DLPC2607

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Typical Current and Power Dissipation
    6. 6.6  I/O Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  Parallel I/F Frame Timing Requirements
    9. 6.9  Parallel I/F General Timing Requirements
    10. 6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
    11. 6.11 BT.656 I/F General Timing Requirements
    12. 6.12 100- to 120-Hz Operational Limitations
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 mDDR Memory Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Parallel Bus Interface
      2. 7.3.2 100- to 120-Hz 3-D Display Operation
    4. 7.4 Programming
      1. 7.4.1 Serial Flash Interface
      2. 7.4.2 Serial Flash Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 System Functional Modes
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Reference Clock
        2. 8.2.2.2 mDDR DRAM Compatibility
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Hot-Plug Usage
        2. 8.2.3.2 Maximum Signal Transition Time
        3. 8.2.3.3 Configuration Control
        4. 8.2.3.4 White Point Correction Light Sensor
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 System Power I/O State Considerations
    4. 9.4 Power-Up Initialization Sequence
    5. 9.5 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  Internal ASIC PLL Power
      2. 10.1.2  General Handling Guidelines for Unused CMOS-Type Pins
      3. 10.1.3  SPI Signal Routing
      4. 10.1.4  mDDR Memory and DMD Interface Considerations
      5. 10.1.5  PCB Design
      6. 10.1.6  General PCB Routing (Applies to All Corresponding PCB Signals)
      7. 10.1.7  Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
      8. 10.1.8  I/F Specific PCB Routing
      9. 10.1.9  Number of Layer Changes
      10. 10.1.10 Stubs
      11. 10.1.11 Termination Requirements:
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Marking
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZVB|176
Thermal pad, mechanical data (Package|Pins)

7.4.1 Serial Flash Interface

The DLPC2607 device uses an external SPI serial flash memory device for configuration support. The minimum required size depends on the desired minimum number of sequences, CMT tables, and splash options while the maximum supported is 16 Mb. Table 1 provides the list of the configuration options.

Table 1. Serial Flash Support Features by Density(1)

TARGET FLASH DENSITY (Mb) QUANTITY OF FEATURES THAT CAN BE SUPPORTED
OPTICAL TEST SPLASH SCREENS STANDARD SPLASH SCREENS SERIES DATA SECTOR UNIT DATA SECTOR ODM DATA SECTOR DLP DISPLAY SEQUENCES (2) CMT TABLES PER SEQUENCE (3)
4 Mb 0 1 1 1 1 16 7
8 Mb 0 3 1 1 1 16 7
16 Mb 1 4 1 1 1 16 7
(1) All rows in this table have passed DVT at TI.
(2) Assumes individual DLP display sequences are limited to 5 KB each
(3) An equal number of CMT tables are required for each sequence (CMT tables define the DeGamma Curve). The DLPC2607 device uses a single SPI, employing SPI mode 0 protocol, operating at a frequency of 33.3 MHz. It supports two independent SPI chip selects. However, the primary flash must be connected to SPI chip select 0 (SPICS0) because the auto-initialization routine is always executed from the device connected to this chip select. The auto-initialization routine executed from flash consists of the following:
  • The DLPC2607 device first uploads the size and location of the auto-initialization routine from address range 0x0000 through 0x0007 of the serial flash memory connected to SPICS0.
  • The DLPC2607 device then uploads the actual auto-initialization routine to its ICP program memory from the serial flash memory connected to SPICS0.
  • The DLPC2607 device then executes an auto-init routine, which includes uploading default control parameter values, uploading mailbox memory contents, turning on the sequence and LEDs, and then enabling the display.
  • Upon completion of the auto-initialization routine, the DLPC2607 signals INIT DONE with GPIO4_INTF.

The DLPC2607 device supports any flash device that is compatible with these modes of operation. However, the DLPC2607 device does not support the Normal (slow) Read Opcode, and thus cannot automatically adapt protocol and clock rate based on the flash’s electronic signature ID. The flash instead uses a fixed SPI clock and assumes certain attributes of the flash have been ensured by PCB design. The DLPC2607 device also assumes the flash supports address auto-incrementing for all read operations. Table 2 and Table 3 list the specific instruction OpCode and timing compatibility requirements for a DLPC2607 device compatible flash.

Table 2. SPI Flash Instruction OpCode and Timing Compatibility Requirements

SPI FLASH COMMAND OPCODE (hex) ADDRESS BYTES DUMMY BYTES MIN CLOCK RATE
Fast READ (single output) 0x0B 3 1 33.3 MHz
All others Can vary Can vary Can vary 33.3 MHz

Table 3. SPI Flash Key Timing Parameter Compatibility Requirements

MIN MAX UNIT
Minimum chip select high time 300 ns
Minimum output hold time 0 ns
Maximum output valid time 9 ns
Minimum data in setup time 5 ns
Minimum data in hold time 5 ns

The DLPC2607 device does not have any specific page, block, or sector size requirements, except that programming with the I2C interface requires the use of page mode programming. However, if the user would like to use a portion of the serial flash for storing external data (such as calibration data) with the I2C interface, then the minimum sector size must be considered as it drives minimum erase size. Note that use of serial flash for storing external data may impact the number of features that can be supported.

NOTE

The DLPC2607 device does not drive the HOLD (active low hold) or WP (active low write protect) pins on the flash device. Tie these pins to a logic high on the PCB with an external pullup.

The DLPC2607 device supports 1.8 V, 2.5 V, or 3.3 V serial flash devices. Some suggested devices would include the W25Q16DWSSIG or MX25U4035. If a different flash device is used, Table 4 lists the minimum performance specifications necessary.

Table 4. Specifications of Compatible SPI Serial Flash Devices

SPI Flash Timing Parameter MIN MAX
Minimum Chip Select High Time 300ns
Minimum Output Hold Time 0ns
Maximum Output Valid Time 9ns
Minimum Data in Setup Time 5ns
Minimum Data in Hold Time 5ns
Minimum Clock Rate 33.3MHz