DLPS023C January   2012  – August 2015 DLPC300

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  I/O Electrical Characteristics
    6. 6.6  Crystal Port Electrical Characteristics
    7. 6.7  Power Consumption
    8. 6.8  I2C Interface Timing Requirements
    9. 6.9  Parallel Interface Frame Timing Requirements
    10. 6.10 Parallel Interface General Timing Requirements
    11. 6.11 Parallel I/F Maximum Supported Horizontal Line Rate
    12. 6.12 BT.565 I/F General Timing Requirements
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 Mobile Dual Data Rate (mDDR) Memory Interface Timing Requirements
    16. 6.16 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Control
      2. 7.4.2 Parallel Bus Interface
      3. 7.4.3 BT.656 Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 System Input Interfaces
          1. 8.2.2.1.1 Control Interface
        2. 8.2.2.2 Input Data Interface
        3. 8.2.2.3 System Output Interfaces
          1. 8.2.2.3.1 Illumination Interface
        4. 8.2.2.4 System Support Interfaces
          1. 8.2.2.4.1 Mobile DDR Synchronous Dram (MDDR)
          2. 8.2.2.4.2 Flash Memory Interface
          3. 8.2.2.4.3 DLPC300 Reference Clock
        5. 8.2.2.5 DMD Interfaces
          1. 8.2.2.5.1 DLPC300 to DLP3000 Digital Data
          2. 8.2.2.5.2 DLPC300 to DLP3000 Control Interface
          3. 8.2.2.5.3 DLPC300 to DLP3000 Micromirror Reset Control Interface
        6. 8.2.2.6 Maximum Signal Transition Time
    3. 8.3 System Examples
      1. 8.3.1 Video Source System Application
      2. 8.3.2 High Pattern Rate System With Optional Fpga
  9. 9 Power Supply Recommendations
    1. 9.1 System Power-Up and Power-Down Sequence
      1. 9.1.1 Power Up Sequence
      2. 9.1.2 Power Down Sequence
      3. 9.1.3 Additional Power-Up Initialization Sequence Details
    2. 9.2 System Power I/O State Considerations
    3. 9.3 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Printed Circuit Board Design Guidelines
      2. 10.1.2 Printed Circuit Board Layer Stackup Geometry
      3. 10.1.3 Signal Layers
      4. 10.1.4 Routing Constraints
      5. 10.1.5 Termination Requirements
      6. 10.1.6 PLL
      7. 10.1.7 General Handling Guidelines for Unused CMOS-Type Pins
      8. 10.1.8 Hot-Plug Usage
      9. 10.1.9 External Clock Input Crystal Oscillator
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Marking
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZVB|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Device Nomenclature

Figure 24 provides a legend for reading the complete device name for any DLP device.

DLPC300 Device_Nomenclature_LPS023.gifFigure 24. Device Nomenclature

11.1.3 Device Marking

The device marking consists of the fields shown in Figure 25.

DLPC300 Device_Symbolization_LPS023.gifFigure 25. Device Marking

11.2 Documentation Support

11.2.1 Related Documentation

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.