DLPS231B October   2021  – October 2024 DLPC3421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 5.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 5.9  DMD Low-Speed Interface Electrical Characteristics
    10. 5.10 System Oscillator Timing Requirements
    11. 5.11 Power Supply and Reset Timing Requirements
    12. 5.12 Parallel Interface Video Frame Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 DSI Host Timing Requirements
    15. 5.15 Flash Interface Timing Requirements
    16. 5.16 Other Timing Requirements
    17. 5.17 DMD Sub-LVDS Interface Switching Characteristics
    18. 5.18 DMD Parking Switching Characteristics
    19. 5.19 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Source Requirements
        1. 6.3.1.1 Supported Resolution and Frame Rates
        2. 6.3.1.2 3D Display
        3. 6.3.1.3 Parallel Interface
          1. 6.3.1.3.1 PDATA Bus - Parallel Interface Bit Mapping Modes
        4. 6.3.1.4 DSI Interface
      2. 6.3.2 Device Startup
      3. 6.3.3 SPI Flash
        1. 6.3.3.1 SPI Flash Interface
        2. 6.3.3.2 SPI Flash Programming
      4. 6.3.4 I2C Interface
      5. 6.3.5 Content Adaptive Illumination Control (CAIC)
      6. 6.3.6 3D Glasses Operation
        1. 6.3.6.1 43
      7. 6.3.7 Test Point Support
      8. 6.3.8 DMD Interface
        1. 6.3.8.1 Sub-LVDS (HS) Interface
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
    6. 6.6 Features and System Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application—nHD Mode
      2. 7.2.2 Typical Application—HD Mode
      3. 7.2.3 Design Requirements
      4. 7.2.4 Detailed Design Procedure
      5. 7.2.5 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 PLL Design Considerations
    2. 8.2 System Power-Up and Power-Down Sequence
    3. 8.3 Power-Up Initialization Sequence
    4. 8.4 DMD Fast Park Control (PARKZ)
    5. 8.5 Hot Plug I/O Usage
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  PLL Power Layout
      2. 9.1.2  Reference Clock Layout
        1. 9.1.2.1 Recommended Crystal Oscillator Configuration
      3. 9.1.3  DSI Interface Layout
      4. 9.1.4  Unused Pins
      5. 9.1.5  DMD Control and SubLVDS Signals
      6. 9.1.6  Layer Changes
      7. 9.1.7  Stubs
      8. 9.1.8  Terminations
      9. 9.1.9  Routing Vias
      10. 9.1.10 Thermal Considerations
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
      3. 10.1.3 Video Timing Parameter Definitions
    2. 10.2 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
  14. 13Package Option Addendum
    1. 13.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

6.3.1.4 DSI Interface

The DLPC34xx controller supports the industry standard DSI (Display Serial Interface) Type-3 LVDS video interface with up to four lanes. DSI is a source-synchronous, high-speed, low-power, low-cost physical layer. The DSI-PHY unit receives data when it operates in high-speed (HS) mode. The DSI-PHY unit receives and transmits data when it operates in low-power (LP) mode for unidirectional data lanes. Point-to-point lane interconnect can be used for either data or clock signal transmission. The high-speed receiver is a differential line receiver circuit. The low-power receiver is an unterminated, single-ended receiver circuit. Figure 6-6 shows a high-level view of the DSI interface.

For a given frame rate, the DSI high-speed (HS) clock frequency must be fixed. If a different DSI clock frequency is ever needed (such as to support another frame rate), an I2C command must be sent to the controller with the updated HS clock frequency.

MIPI refers to the Mobile Industry Processor Interface standard.

Various DSI requirements and features of the DLPC34xx are as follows:

  • compliant with the DSI-MIPI Specification for Display Serial Interface (V 1.02.00) except for those items noted in the DSI Host Timing Requirements table
  • compliant with D-PHY standard MIPI Specification (V 1.0)
  • MIPI DSI Type 3 architecture
  • supports display resolutions shown in Section 6.3.1.1
  • supports video mode (command mode not supported)
  • MIPI DCSSM (Display Command SetSM) commands sent over DSI not supported (send commands via I2C instead)
  • supports multiple packets per transmission
  • supports trigger messages in the forward direction
  • data lanes configurable from one to four channels
  • EOT (End of Transfer) command is supported and must be enabled
  • CRC (cyclic redundancy check) and ECC (error correction code) for header supported
    • CRC and ECC can be disabled
  • checksum for long packets with error reporting (but no ECC)
  • supports one virtual channel for video mode
  • supports burst mode
  • supports non-burst with sync pulses and with sync event
  • BTA (bus turn-around) mode not supported and must be disabled in the DSI host processor
  • LP mode is required during vertical blanking and vertical sync. LP mode is not supported between pixel lines (i.e. HS blanking must be used for horizontal blanking and horizontal sync)
  • an active DSI HS clock is required during LP blanking
DLPC3421 DSI High Level View
- one clock lane
- one bi-directional data lane (Data0)
- up to three additional uni-directional data lanes (Data1, Data2, and Data3)
Figure 6-6 DSI High Level View

The differential DSI clock lane (DCLKN and DCLKP) must be in the LP11 (Idle) state upon the de-assertion of RESETZ (zero-to-one transition) and must remain in this state until HOST_IRQ is de-asserted (one-to-zero transition) to ensure proper DSI initialization.

The controller requires differential data lane '0' (DD0N:DD0P) for DSI operation. The three remaining data lanes are optional depending on the desired input resolution and frame rate. Not all display resolutions and frame rates are supported without using all four data lanes.

The state of GPIO (2:1) pins upon the de-assertion of RESETZ (zero-to-one transition) determines the number of DSI data lanes that are enabled for both LP and HS bus operation.

DSI supported data transfer formats are as follows:

  • 24-bit RGB888 - each pixel uses 3 bytes
  • 18-bit RGB666 - each pixel packed into 2 or more bytes
  • 18-bit RGB666 - each pixel loosely packed into 3 bytes
  • 16-bit 4:2:2 YCbCr - each pixel uses 2 bytes