DLPS231B October   2021  – October 2024 DLPC3421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 5.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 5.9  DMD Low-Speed Interface Electrical Characteristics
    10. 5.10 System Oscillator Timing Requirements
    11. 5.11 Power Supply and Reset Timing Requirements
    12. 5.12 Parallel Interface Video Frame Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 DSI Host Timing Requirements
    15. 5.15 Flash Interface Timing Requirements
    16. 5.16 Other Timing Requirements
    17. 5.17 DMD Sub-LVDS Interface Switching Characteristics
    18. 5.18 DMD Parking Switching Characteristics
    19. 5.19 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Source Requirements
        1. 6.3.1.1 Supported Resolution and Frame Rates
        2. 6.3.1.2 3D Display
        3. 6.3.1.3 Parallel Interface
          1. 6.3.1.3.1 PDATA Bus - Parallel Interface Bit Mapping Modes
        4. 6.3.1.4 DSI Interface
      2. 6.3.2 Device Startup
      3. 6.3.3 SPI Flash
        1. 6.3.3.1 SPI Flash Interface
        2. 6.3.3.2 SPI Flash Programming
      4. 6.3.4 I2C Interface
      5. 6.3.5 Content Adaptive Illumination Control (CAIC)
      6. 6.3.6 3D Glasses Operation
        1. 6.3.6.1 43
      7. 6.3.7 Test Point Support
      8. 6.3.8 DMD Interface
        1. 6.3.8.1 Sub-LVDS (HS) Interface
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
    6. 6.6 Features and System Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application—nHD Mode
      2. 7.2.2 Typical Application—HD Mode
      3. 7.2.3 Design Requirements
      4. 7.2.4 Detailed Design Procedure
      5. 7.2.5 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 PLL Design Considerations
    2. 8.2 System Power-Up and Power-Down Sequence
    3. 8.3 Power-Up Initialization Sequence
    4. 8.4 DMD Fast Park Control (PARKZ)
    5. 8.5 Hot Plug I/O Usage
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  PLL Power Layout
      2. 9.1.2  Reference Clock Layout
        1. 9.1.2.1 Recommended Crystal Oscillator Configuration
      3. 9.1.3  DSI Interface Layout
      4. 9.1.4  Unused Pins
      5. 9.1.5  DMD Control and SubLVDS Signals
      6. 9.1.6  Layer Changes
      7. 9.1.7  Stubs
      8. 9.1.8  Terminations
      9. 9.1.9  Routing Vias
      10. 9.1.10 Thermal Considerations
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
      3. 10.1.3 Video Timing Parameter Definitions
    2. 10.2 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
  14. 13Package Option Addendum
    1. 13.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

9.1.5 DMD Control and SubLVDS Signals

Table 9-4 Maximum Pin-to-Pin PCB Interconnect Recommendations
DMD BUS SIGNAL(1)(2)SIGNAL INTERCONNECT TOPOLOGYUNIT
SINGLE-BOARD SIGNAL ROUTING LENGTHMULTI-BOARD SIGNAL ROUTING LENGTH
DMD_HS_CLK_P
DMD_HS_CLK_N		6.0
(152.4)		See (3)in
(mm)
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N		 6.0
(152.4)		 See (3) in
mm
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_LS_CLK6.5
(165.1)		See (3)in
(mm)
DMD_LS_WDATA6.5
(165.1)		See (3)in
(mm)
DMD_LS_RDATA6.5
(165.1)		See (3)in
(mm)
DMD_DEN_ARSTZ7.0
(177.8)		See (3)in
(mm)
(1) Maximum signal routing length includes escape routing.
(2) Multiboard DMD routing length is more restricted due to the impact of the connector.
(3) Due to PCB variations, these recommendations cannot be defined. Any board design should SPICE simulate with the controller IBIS model (found under the Tools & Software tab of the controller web page) to ensure routing lengths do not violate signal requirements.
Table 9-5 High Speed PCB Signal Routing Matching Requirements
SIGNAL GROUP LENGTH MATCHING(1)(2)(3)
INTERFACESIGNAL GROUPREFERENCE SIGNALMAX MISMATCH(4)UNIT
DMD(5)DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N		DMD_HS_CLK_P
DMD_HS_CLK_N		±1.0
(±25.4)		in
(mm)
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMDDMD_HS_WDATA_x_PDMD_HS_WDATA_x_N±0.025
(±0.635)		in
(mm)
DMDDMD_HS_CLK_PDMD_HS_CLK_N±0.025
(±0.635)		in
(mm)
DMDDMD_LS_WDATA
DMD_LS_RDATA		DMD_LS_CLK±0.2
(±5.08)		in
(mm)
DMDDMD_DEN_ARSTZN/AN/Ain
(mm)
(1) The length matching values apply to PCB routing lengths only. Internal package routing mismatch associated with the DLPC34xx controller or the DMD require no additional consideration.
(2) Training is applied to DMD HS data lines. This is why the defined matching requirements are slightly relaxed compared to the LS data lines.
(3) DMD LS signals are single ended.
(4) Mismatch variance for a signal group is always with respect to the reference signal.
(5) DMD HS data lines are differential; thus, these specifications are pair-to-pair.
Table 9-6 Signal Requirements
PARAMETERREFERENCEREQUIREMENT
Source series terminationDMD_LS_WDATARequired
DMD_LS_CLKRequired
DMD_DEN_ARSTZAcceptable
DMD_LS_RDATARequired
DMD_HS_WDATA_x_yNot acceptable
DMD_HS_CLK_yNot acceptable
Endpoint terminationDMD_LS_WDATANot acceptable
DMD_LS_CLKNot acceptable
DMD_DEN_ARSTZNot acceptable
DMD_LS_RDATANot acceptable
DMD_HS_WDATA_x_yNot acceptable
DMD_HS_CLK_yNot acceptable
PCB impedanceDMD_LS_WDATA68Ω ±10%
DMD_LS_CLK68Ω ±10%
DMD_DEN_ARSTZ68Ω ±10%
DMD_LS_RDATA68Ω ±10%
DMD_HS_WDATA_x_y100Ω ±10%
DMD_HS_CLK_y100Ω ±10%
Signal typeDMD_LS_WDATASDR (single data rate) referenced to DMD_LS_DCLK
DMD_LS_CLKSDR referenced to DMD_LS_DCLK
DMD_DEN_ARSTZSDR
DMD_LS_RDATASDR referenced to DMD_LS_DLCK
DMD_HS_WDATA_x_ySubLVDS
DMD_HS_CLK_ySubLVDS