DLPS231B October   2021  – October 2024 DLPC3421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 5.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 5.9  DMD Low-Speed Interface Electrical Characteristics
    10. 5.10 System Oscillator Timing Requirements
    11. 5.11 Power Supply and Reset Timing Requirements
    12. 5.12 Parallel Interface Video Frame Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 DSI Host Timing Requirements
    15. 5.15 Flash Interface Timing Requirements
    16. 5.16 Other Timing Requirements
    17. 5.17 DMD Sub-LVDS Interface Switching Characteristics
    18. 5.18 DMD Parking Switching Characteristics
    19. 5.19 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Source Requirements
        1. 6.3.1.1 Supported Resolution and Frame Rates
        2. 6.3.1.2 3D Display
        3. 6.3.1.3 Parallel Interface
          1. 6.3.1.3.1 PDATA Bus - Parallel Interface Bit Mapping Modes
        4. 6.3.1.4 DSI Interface
      2. 6.3.2 Device Startup
      3. 6.3.3 SPI Flash
        1. 6.3.3.1 SPI Flash Interface
        2. 6.3.3.2 SPI Flash Programming
      4. 6.3.4 I2C Interface
      5. 6.3.5 Content Adaptive Illumination Control (CAIC)
      6. 6.3.6 3D Glasses Operation
        1. 6.3.6.1 43
      7. 6.3.7 Test Point Support
      8. 6.3.8 DMD Interface
        1. 6.3.8.1 Sub-LVDS (HS) Interface
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
    6. 6.6 Features and System Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application—nHD Mode
      2. 7.2.2 Typical Application—HD Mode
      3. 7.2.3 Design Requirements
      4. 7.2.4 Detailed Design Procedure
      5. 7.2.5 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 PLL Design Considerations
    2. 8.2 System Power-Up and Power-Down Sequence
    3. 8.3 Power-Up Initialization Sequence
    4. 8.4 DMD Fast Park Control (PARKZ)
    5. 8.5 Hot Plug I/O Usage
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  PLL Power Layout
      2. 9.1.2  Reference Clock Layout
        1. 9.1.2.1 Recommended Crystal Oscillator Configuration
      3. 9.1.3  DSI Interface Layout
      4. 9.1.4  Unused Pins
      5. 9.1.5  DMD Control and SubLVDS Signals
      6. 9.1.6  Layer Changes
      7. 9.1.7  Stubs
      8. 9.1.8  Terminations
      9. 9.1.9  Routing Vias
      10. 9.1.10 Thermal Considerations
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
      3. 10.1.3 Video Timing Parameter Definitions
    2. 10.2 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
  14. 13Package Option Addendum
    1. 13.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

5.7 Internal Pullup and Pulldown Electrical Characteristics

over operating free-air temperature (unless otherwise noted)(2)
INTERNAL PULLUP AND PULLDOWN RESISTOR CHARACTERISTICSTEST CONDITIONS(1)MINMAXUNIT
Weak pullup resistanceVCCIO = 3.3V2963kΩ
VCCIO = 2.5V3890
VCCIO = 1.8V56148
Weak pulldown resistanceVCCIO = 3.3V3072kΩ
VCCIO = 2.5V36101
VCCIO = 1.8V52167
(1) The resistance is dependent on VCCIO, the pin's supply reference (see a given pins supply reference in Table 4-11).
(2) An external 8-kΩ pullup or pulldown (if needed) would work for any voltage condition to correctly pull enough to override any associated internal pullups or pulldowns.