DLPS231B October   2021  – October 2024 DLPC3421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 5.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 5.9  DMD Low-Speed Interface Electrical Characteristics
    10. 5.10 System Oscillator Timing Requirements
    11. 5.11 Power Supply and Reset Timing Requirements
    12. 5.12 Parallel Interface Video Frame Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 DSI Host Timing Requirements
    15. 5.15 Flash Interface Timing Requirements
    16. 5.16 Other Timing Requirements
    17. 5.17 DMD Sub-LVDS Interface Switching Characteristics
    18. 5.18 DMD Parking Switching Characteristics
    19. 5.19 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Source Requirements
        1. 6.3.1.1 Supported Resolution and Frame Rates
        2. 6.3.1.2 3D Display
        3. 6.3.1.3 Parallel Interface
          1. 6.3.1.3.1 PDATA Bus - Parallel Interface Bit Mapping Modes
        4. 6.3.1.4 DSI Interface
      2. 6.3.2 Device Startup
      3. 6.3.3 SPI Flash
        1. 6.3.3.1 SPI Flash Interface
        2. 6.3.3.2 SPI Flash Programming
      4. 6.3.4 I2C Interface
      5. 6.3.5 Content Adaptive Illumination Control (CAIC)
      6. 6.3.6 3D Glasses Operation
        1. 6.3.6.1 43
      7. 6.3.7 Test Point Support
      8. 6.3.8 DMD Interface
        1. 6.3.8.1 Sub-LVDS (HS) Interface
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
    6. 6.6 Features and System Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application—nHD Mode
      2. 7.2.2 Typical Application—HD Mode
      3. 7.2.3 Design Requirements
      4. 7.2.4 Detailed Design Procedure
      5. 7.2.5 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 PLL Design Considerations
    2. 8.2 System Power-Up and Power-Down Sequence
    3. 8.3 Power-Up Initialization Sequence
    4. 8.4 DMD Fast Park Control (PARKZ)
    5. 8.5 Hot Plug I/O Usage
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  PLL Power Layout
      2. 9.1.2  Reference Clock Layout
        1. 9.1.2.1 Recommended Crystal Oscillator Configuration
      3. 9.1.3  DSI Interface Layout
      4. 9.1.4  Unused Pins
      5. 9.1.5  DMD Control and SubLVDS Signals
      6. 9.1.6  Layer Changes
      7. 9.1.7  Stubs
      8. 9.1.8  Terminations
      9. 9.1.9  Routing Vias
      10. 9.1.10 Thermal Considerations
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
      3. 10.1.3 Video Timing Parameter Definitions
    2. 10.2 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
  14. 13Package Option Addendum
    1. 13.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

5.5 Power Electrical Characteristics

Table 5-1 nHD Mode over free-air temperature range (unless otherwise noted)
PARAMETER(1)(2)(3) TEST CONDITIONS MIN TYP(4) MAX(5) UNIT
I(VDD) + I(VDD_PLLM) + I(VDD_PLLD) 1.1V rails Frame rate = 60Hz 81 109 mA
Frame rate = 120Hz 85 128
Frame rate = 240Hz 115 167
Frame rate = 360Hz 150 205
I(VDD_PLLM) MCG PLL 1.1V current6 Frame rate = 60Hz 6 mA
Frame rate = 120Hz 6
Frame rate = 240Hz 6
Frame rate = 360Hz 6
I(VDD_PLLD) DCG PLL 1.1V current6 Frame rate = 60Hz 6 mA
Frame rate = 120Hz 6
Frame rate = 240Hz 6
Frame rate = 360Hz 6
I(VCC18) All 1.8V I/O current: (1.8V power supply for all I/O other than the host or parallel interface and the SPI flash interface) Frame rate = 60Hz 21.2 26.5 mA
Frame rate = 120Hz 21.2 26.5
Frame rate = 240Hz 21.3 26.3
Frame rate = 360Hz 19.9 23.9
I(VCC_INTF) Host or parallel interface I/O current: 1.8 to 3.3 V (includes IIC0, PDATA, video syncs, and HOST_IRQ pins)6 Frame rate = 60Hz 2 mA
Frame rate = 120Hz 2
Frame rate = 240Hz 2
Frame rate = 360Hz 2
I(VCC_FLSH) Flash interface I/O current: 1.8 to 3.3 V6 Frame rate = 60Hz 1 mA
Frame rate = 120Hz 1
Frame rate = 240Hz 1
Frame rate = 360Hz 1
(1) Values assume all pins using 1.1V are tied together (including VDDLP12), and programmable host and flash I/O are at the minimum nominal voltage (that is 1.8V).
(2) Input image is 640 × 360 (nHD) 24 bits using VESA reduced blanking v2 timings on the parallel interface at the frame rate shown with the 0.16in HD and nHD (DLP160CP) DMD. The controller has the CAIC and LABB algorithms turned off.
(3) The values do not take into account software updates or customer changes that may affect power performance.
(4) Assumes nominal process, voltage, and temperature (25°C nominal ambient) with SMPTE color bar as the nominal input image.
(5) Assumes worst case process, maximum voltage, and high nominal ambient temperature of 65°C with worst case input image.
(6) This rail was not measured due to board limitations. Simulation values are used instead. Simulations assume 12.5% activity factor, 30% clock gating on appropriate domains, and mixed SVT (standard threshold voltage) or HVT (high threshold voltage) cells
Table 5-2 HD Mode over free-air temperature range (unless otherwise noted)
PARAMETER(1)(2)(3) TEST CONDITIONS MIN TYP(4) MAX(5) UNIT
I(VDD) + I(VDD_PLLM) + I(VDD_PLLD) 1.1V rails Frame rate = 50Hz 106 151 mA
Frame rate = 60Hz 115 168
I(VDD_PLLM) MCG PLL 1.1V current6 Frame rate = 50Hz 6 mA
Frame rate = 60Hz 6
I(VDD_PLLD) DCG PLL 1.1V current6 Frame rate = 50Hz 6 mA
Frame rate = 60Hz 6
I(VCC18) All 1.8V I/O current: (1.8V power supply for all I/O other than the host or parallel interface and the SPI flash interface) Frame rate = 50Hz 19.3 23.5 mA
Frame rate = 60Hz 21.3 26.3
I(VCC_INTF) Host or parallel interface I/O current: 1.8 to 3.3 V (includes IIC0, PDATA, video syncs, and HOST_IRQ pins)6 Frame rate = 50Hz 2 mA
Frame rate = 60Hz 2
I(VCC_FLSH) Flash interface I/O current: 1.8 to 3.3 V6 Frame rate = 50Hz 1 mA
Frame rate = 60Hz 1