DLPS156F January   2019  – November 2024 DLPC3436

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Test Pins and General Control
    2. 4.2 Parallel Port Input
    3. 4.3 DSI Input Data and Clock
    4. 4.4 DMD Reset and Bias Control
    5. 4.5 DMD SubLVDS Interface
    6. 4.6 Peripheral Interface
    7. 4.7 GPIO Peripheral Interface
    8. 4.8 Clock and PLL Support
    9. 4.9 Power and Ground
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 5.8  DMD SubLVDS Interface Electrical Characteristics
    9. 5.9  DMD Low-Speed Interface Electrical Characteristics
    10. 5.10 System Oscillator Timing Requirements
    11. 5.11 Power Supply and Reset Timing Requirements
    12. 5.12 Parallel Interface Frame Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 Flash Interface Timing Requirements
    15. 5.15 Other Timing Requirements
    16. 5.16 DMD SubLVDS Interface Switching Characteristics
    17. 5.17 DMD Parking Switching Characteristics
    18. 5.18 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Source Requirements
        1. 6.3.1.1 Input Frame Rates and 3-D Display Operation
          1. 6.3.1.1.1 Parallel Interface Data Transfer Format
        2. 6.3.1.2 3D Display
      2. 6.3.2 Device Startup
      3. 6.3.3 SPI Flash
        1. 6.3.3.1 SPI Flash Interface
        2. 6.3.3.2 SPI Flash Programming
      4. 6.3.4 I2C Interface
      5. 6.3.5 Content Adaptive Illumination Control (CAIC)
      6. 6.3.6 Local Area Brightness Boost (LABB)
      7. 6.3.7 3D Glasses Operation
      8. 6.3.8 Test Point Support
      9. 6.3.9 DMD Interface
        1. 6.3.9.1 SubLVDS (HS) Interface
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 PLL Design Considerations
    2. 8.2 System Power-Up and Power-Down Sequence
    3. 8.3 Power-Up Initialization Sequence
    4. 8.4 DMD Fast Park Control (PARKZ)
    5. 8.5 Hot Plug I/O Usage
    6. 8.6 Maximum Signal Transition Time
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 PLL Power Layout
      2. 9.1.2 Reference Clock Layout
        1. 9.1.2.1 Recommended Crystal Oscillator Configuration
      3. 9.1.3 Unused Pins
      4. 9.1.4 DMD Control and SubLVDS Signals
      5. 9.1.5 Layer Changes
      6. 9.1.6 Stubs
      7. 9.1.7 Terminations
      8. 9.1.8 Routing Vias
      9. 9.1.9 Thermal Considerations
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings DLPC343x
        2. 10.1.2.2 Device Markings DLPC342x
        3. 10.1.2.3 Video Timing Parameter Definitions
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1.1 Input Frame Rates and 3-D Display Operation

Table 6-1 Supported Input Source Ranges (to FPGA)(1)(2)(3)
INTERFACE BITS PER PIXEL (max)(4) IMAGE TYPE SOURCE RESOLUTION RANGE(5) FRAME RATE RANGE
HORIZONTAL VERTICAL
Landscape Portrait Landscape Portrait
Parallel 24 2D - qHD 960 N/A 540 N/A 50 ± 2 Hz,
60 ± 2 Hz,
100 ± 2 Hz,
120 ± 2 Hz,
200 ± 2 Hz,
240 ± 2 Hz
Parallel 24 2D - 1080p 1920 N/A 1080 N/A 50 ± 2 Hz,
60 ± 2 Hz
Parallel 24 3D - qHD(6) 960 N/A 540 N/A 100 ± 2 Hz,
120 ± 2 Hz
(1) The application must remain within specifications for all source interface parameters such as maximum clock rate and maximum line rate.
(2) The maximum DMD pixel display resolution is 1920 × 1080 while system actuator is enabled.
(3) To achieve the ranges stated, the firmware must support the source parameters. Review the firmware release notes or contact TI to determine the latest available frame rate and input resolution support for a given firmware image.
(4) Bits per pixel does not necessarily equal the number of data pins used on the DLPC34xx controller. Fewer pins are used if multiple clocks are used per pixel transfer.
(5) The DLPC34x6 only supports landscape orientation.
(6) 3D video is formatted as frame sequential.
Table 6-2 Supported FPGA Input Interface
INTERFACE IMAGE TYPE XC7Z020-1CLG484I4493 XC7S50-2CSGA324C4493
Parallel 2D - qHD Supported Not Supported
Parallel 2D - 1080p Supported Not Supported
Parallel 3D - qHD Supported Not Supported
FPD-Link 2D - qHD Supported Supported
FPD-Link 2D - 1080p Supported Supported
FPD-Link 3D - qHD Supported Supported

The DLPC34x6 supports both 2D and 3D sources on the parallel interface. The frame and sub-frame timing for 2D sources is shown in Figure 6-1 while the frame timing for 3D sources is shown in Figure 6-3.

DLPC3436 2D Actuator Frame and Signal Timing Figure 6-1 2D Actuator Frame and Signal Timing