DLPS084D January   2017  – August 2021 DLPC3437

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillators Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 3D Display
        3. 7.3.1.3 Parallel Interface
          1. 7.3.1.3.1 Parallel Interface Data Transfer Format
      2. 7.3.2 Device Start-Up
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast PARK Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

9.2 System Power-Up and Power-Down Sequence

Although the DLPC3437 requires an array of power supply voltages, (for example, VDD, VDDLP12, VDD_PLLM/D, VCC18, VCC_FLSH, VCC_INTF), since VDDLP12 is tied to the 1.1-V VDD supply, then there are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC3437 (true for both power-up and power-down scenarios). Similarly, there is no minimum time between powering-up or powering-down the different supplies if VDDLP12 is tied to the 1.1-V VDD supply.

Although there is no risk of damaging the DLPC3437 if the above power sequencing rules are followed, the following additional power sequencing recommendations must be considered to ensure proper system operation.

  • To ensure that DLPC3437 output signal states behave as expected, all DLPC3437 I/O supplies must remain applied while VDD core power is applied. If VDD core power is removed while the I/O supply (VCC_INTF) is applied, then the output signal state associated with the inactive I/O supply goes into a high impedance state.
  • Additional power sequencing rules can exist for devices that share the supplies with the DLPC3437, and thus these devices may force additional system power sequencing requirements.

Note that when VDD core power is applied, but I/O power is not applied, additional leakage current may be drawn. This added leakage does not affect normal DLPC3437 operation or reliability.

Figure 9-1 and Figure 9-2 show the DLPC3437 power-up and power-down sequence for both the normal PARK and fast PARK operations of the DLPC3437 controller.

Note:

During a Normal Park, it is recommended to maintain SYSPWR within specification for at least 50 ms after PROJ_ON goes low to allow the DMD to be parked and the power supply rails to safely power down. After 50 ms, SYSPWR can be turned off. If a DLPA200x is used, it is also recommended that the 1.8-V supply fed into the DLPA200x load switch be maintained within specification for at least 50 ms after PROJ_ON goes low.

Figure 9-1 DLPC3437 Power-Up Timing
t1: (VIN) applied to the PMIC. All other voltage rails are derived from SYSPWR.
t2: All supplies reach 95% of their specified nominal value. Note HOST_IRQ may go high sooner if it is pulled-up to a different external supply.
t3: Point where RESETZ is deasserted (goes high). Indicates the beginning of the controller auto-initialization routine.
t4:

HOST_IRQ goes low to indicate initialization is complete. I2C is now ready to accept commands.
(a):

The typical delay between the PLL reference clock becoming active and RESETZ being deasserted (going high) is less than 1 ms. PLL_REFCLK must be stable within 5 ms of all power being applied, and may be active before power is applied.
(b): RESETZ must also be held low for at least 5 ms after the power supplies are in specification.
(c): There is a typical delay of 1.5 s between being FPGA RESETZ being deasserted and FPGA_RDY being asserted (going high). This duration is due to FPGA boot logic.
(d): There is a typical controller boot time of 100 ms. PARKZ must be high before RESETZ releases to support auto-initialization.
(e):

There is a typical FPGA setup time of 2.75 ms before the system completes boot process. During this period, the DLPC3437 controller writes startup values to the FPGA registers. After FPGA setup is complete, I2C now accepts commands.
Figure 9-2 DLPC3437 Normal Power-Down
t1: PROJ_ON goes low to begin the power down sequence.
t2: The controller finishes parking the DMD.
t3: RESETZ is asserted which causes HOST_IRQ to be pulled high.
t4: All controller power supplies are turned off.
t5: SYSPWR is removed now that all other supplies are turned off.
(a): I2C activity must stop before PROJ_ON is deasserted (goes low).
(b): The DMD parks within 20 ms of PROJ_ON being deasserted (going low). VDD, VDD_PLLM/D, VCC18, VCC_INITF, and VCC_FLSH power supplies and the PLL_REFCLK must be held within specification for a minimum of 20 ms after PROJ_ON is deasserted (goes low). However, 20 ms does not satisfy the typical shutdown timing of the entire chipset. Follow note (c).
(c): Do not turn off SYSPWR until at least 50 ms after PROJ_ON is deasserted (goes low). This time allows the DMD to be parked, the controller to turn off, and the PMIC supplies to shut down.
Figure 9-3 DLPC3437 Fast Power-Down
t1: A fault is detected (in this example the PMIC detects a UVLO condition) and PARKZ is asserted (goes low) to tell the controller to initiate a fast park of the DMD.
t2: The controller finishes the fast park procedure.
t3: RESETZ is asserted which puts the controller in a reset state which causes HOST_IRQ to be pulled high.
t4: Eventually all power supplies that were derived from SYSPWR collapse.
(a): VDD, VDD_PLLM/D, VCC18, VCC_INITF, and VCC_FLSH power supplies and the PLL_REFCLK must be held within specification for a minimum of 32 µs after PARKZ is asserted (goes low).
(b): VCC18 must remain in specification long enough to satisfy DMD power sequencing requirements defined in the DMD datasheet. Also see the DLPAxxxx datasheets for more information.