DLPS112C June   2018  – August 2021 DLPC3479

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 3D Display
        3. 7.3.1.3 Parallel Interface
          1. 7.3.1.3.1 PDATA Bus – Parallel Interface Bit Mapping Modes
      2. 7.3.2  Pattern Display
        1. 7.3.2.1 External Pattern Mode
          1. 7.3.2.1.1 8-bit Monochrome Patterns
          2. 7.3.2.1.2 1-Bit Monochrome Patterns
        2. 7.3.2.2 Internal Pattern Mode
          1. 7.3.2.2.1 Free Running Mode
          2. 7.3.2.2.2 Trigger In Mode
      3. 7.3.3  Device Start-Up
      4. 7.3.4  SPI Flash
        1. 7.3.4.1 SPI Flash Interface
        2. 7.3.4.2 SPI Flash Programming
      5. 7.3.5  I2C Interface
      6. 7.3.6  Content Adaptive Illumination Control (CAIC)
      7. 7.3.7  Local Area Brightness Boost (LABB)
      8. 7.3.8  3D Glasses Operation
      9. 7.3.9  Test Point Support
      10. 7.3.10 DMD Interface
        1. 7.3.10.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
      3. 11.1.3 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Pin Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER(3)TEST CONDITIONS(4)MINTYPMAXUNIT
VIHHigh-level input threshold voltageI2C buffer (I/O type 7)0.7 × VCC_INTFSee  (1)V
I/O type 1, 2, 3, 6, 8 except pins noted in (2)VCC18 = 1.8 V1.173.6
I/O type 1, 6 for pins noted in (2)VCC18 = 1.8 V1.33.6
I/O type 5, 9, 11VCC_INTF = 1.8 V1.173.6
I/O type 12, 13VCC_FLSH = 1.8 V1.173.6
I/O type 5, 9, 11VCC_INTF = 2.5 V1.73.6
I/O type 12, 13VCC_FLSH = 2.5 V1.73.6
I/O type 5, 9, 11VCC_INTF = 3.3 V2.03.6
I/O type 12, 13VCC_FLSH = 3.3 V2.03.6
VILLow-level input threshold voltageI2C buffer (I/O type 7)–0.50.3 × VCC_INTFV
I/O type 1, 2, 3, 6, 8 except pins noted in (2)VCC18 = 1.8 V–0.30.63
I/O type 1, 6 for pins noted in (2)VCC18 = 1.8 V–0.30.5
I/O type 5, 9, 11VCC_INTF = 1.8 V–0.30.63
I/O type 12, 13VCC_FLSH = 1.8 V–0.30.63
I/O type 5, 9, 11VCC_INTF = 2.5 V–0.30.7
I/O type 12, 13VCC_FLSH = 2.5 V–0.30.7
I/O type 5, 9, 11VCC_INTF = 3.3 V–0.30.8
I/O type 12, 13VCC_FLSH = 3.3 V–0.30.8
VOHHigh-level output voltageI/O type 1, 2, 3, 6, 8VCC18 = 1.8 V1.35V
I/O type 5, 9, 11VCC_INTF = 1.8 V1.35
I/O type 12, 13VCC_FLSH = 1.8 V1.35
I/O type 5, 9, 11VCC_INTF = 2.5 V1.7
I/O type 12, 13VCC_FLSH = 2.5 V1.7
I/O type 5, 9, 11VCC_INTF = 3.3 V2.4
I/O type 12, 13VCC_FLSH = 3.3 V2.4
VOLLow-level output voltageI2C buffer (I/O type 7)VCC_INTF > 2 V0.4V
I2C buffer (I/O type 7)VCC_INTF < 2 V0.2 × VCC_INTF
I/O type 1, 2, 3, 6, 8VCC18 = 1.8 V0.45
I/O Type 5, 9, 11VCC_INTF = 1.8 V0.45
I/O Type 12, 13VCC_FLSH = 1.8 V0.45
I/O Type 5, 9, 11VCC_INTF = 2.5 V0.7
I/O Type 12, 13VCC_FLSH = 2.5 V0.7
I/O Type 5, 9, 11VCC_INTF = 3.3 V0.4
I/O Type 12, 13VCC_FLSH = 3.3 V0.4
IOHHigh-level output current(5)I/O type 2, 4VCC18 = 1.8 V2mA
I/O type 5VCC_INTF = 1.8 V2
I/O type 1VCC18 = 1.8 V3.5
I/O type 9VCC_INTF = 1.8 V3.5
I/O type 13VCC_FLSH = 1.8 V3.5
I/O type 3VCC18 = 1.8 V10.6
I/O type 5VCC_INTF = 2.5 V5.4
I/O type 9, 13VCC_INTF = 2.5V10.8
I/O type 13VCC_FLSH = 2.5 V10.8
I/O type 5VCC_INTF = 3.3 V7.8
I/O type 9VCC_INTF = 3.3 V15
I/O type 13VCC_FLSH = 3.3 V15
IOLLow-level output current(6)I2C buffer (I/O type 7)3mA
I/O type 2, 4VCC18 = 1.8 V2.3
I/O type 5VCC_INTF = 1.8 V2.3
I/O type 1VCC18 = 1.8 V4.6
I/O type 9VCC_INTF = 1.8 V4.6
I/O type 13VCC_FLSH = 1.8 V4.6
I/O type 3VCC18 = 1.8 V13.9
I/O type 5VCC_INTF = 2.5 V5.2
I/O type 9VCC_INTF = 2.5 V10.4
I/O type 13VCC_FLSH = 2.5 V10.4
I/O type 5VCC_INTF = 3.3 V4.4
I/O type 9VCC_INTF = 3.3 V8.9
I/O type 13VCC_FLSH = 3.3 V8.9
IOZHigh-impedance leakage currentI2C buffer (I/O type 7)VI2C buffer < 0.1 × VCC_INTF or
VI2C buffer > 0.9 × VCC_INTF		–1010µA
I/O type 1, 2, 3, 6, 8,VCC18 = 1.8 V–1010
I/O Type 5, 9, 11VCC_INTF = 1.8 V–1010
I/O Type 12, 13VCC_FLSH = 1.8 V–1010
I/O type 5, 9, 11VCC_INTF = 2.5 V–1010
I/O Type 12, 13VCC_FLSH = 2.5 V–1010
I/O Type 5, 9, 11VCC_INTF = 3.3 V–1010
I/O type 12, 13VCC_FLSH = 3.3 V–1010
CIInput capacitance (including package)I2C buffer (I/O type 7)5pF
I/O type 1, 2, 3, 6, 8VCC18 = 1.8 V2.63.5
I/O Type 5, 9, 11VCC_INTF = 1.8 V2.63.5
I/O Type 12, 13VCC_FLSH = 1.8 V2.63.5
I/O type 5, 9, 11VCC_INTF = 2.5 V2.63.5
I/O type 12, 13VCC_FLSH = 2.5 V2.63.5
I/O type 5, 9, 11VCC_INTF = 3.3 V2.63.5
I/O type 12, 13VCC_FLSH = 3.3 V2.63.5
sub-LVDS – DMD high speed (I/O type 4)VCC18 = 1.8 V3
(1) I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.
(2) Controller pins CMP_OUT, PARKZ, RESETZ, and GPIO_00 through GPIO_19 have slightly varied VIH and VIL range from other 1.8-V I/O.
(3) The I/O type refers to the type defined in Table 5-9.
(4) Test conditions that define a value for VCC18, VCC_INTF, or VCC_FLSH show the nominal voltage that the specified I/O supply reference is set to.
(5) At a high level output signal, the given I/O outputs at least the minimum current specified.
(6) At a low level output signal, the given I/O sinks at least the minimum current specified.