DLPS222A December   2021  – February 2023 DLPC4420

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements
    7. 6.7  Test and Reset Timing Requirements
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  Port 1 Input Pixel Timing Requirements
    10. 6.10 Port 3 Input Pixel Interface (via GPIO) Timing Requirements
    11. 6.11 DMD LVDS Interface Timing Requirements
    12. 6.12 Synchronous Serial Port (SSP) Interface Timing Requirements
    13. 6.13 Programmable Output Clocks Switching Characteristics
    14. 6.14 Synchronous Serial Port Interface (SSP) Switching Characteristics
    15. 6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 System Reset Operation
        1. 7.3.1.1 Power-Up Reset Operation
        2. 7.3.1.2 System Reset Operation
      2. 7.3.2 Spread Spectrum Clock Generator Support
      3. 7.3.3 GPIO Interface
      4. 7.3.4 Source Input Blanking
      5. 7.3.5 Video Graphics Processing Delay
      6. 7.3.6 Program Memory Flash/SRAM Interface
      7. 7.3.7 Calibration and Debug Support
      8. 7.3.8 Board Level Test Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Regulations
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC4420 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.1V System Power
      3. 9.4.3 1.8V System Power
      4. 9.4.4 3.3V System Power
      5. 9.4.5 Power Good (PWRGOOD) Support
      6. 9.4.6 5V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal DLPC4420 Power
      2. 10.1.2 PCB Layout Guidelines for Auto-Lock Performance
      3. 10.1.3 DMD Interface Considerations
      4. 10.1.4 Layout Example
      5. 10.1.5 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Video Timing Parameter Definitions
      2. 11.2.2 Device Nomenclature
      3. 11.2.3 Device Markings
        1. 11.2.3.1 Device Marking
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.2.1 Video Timing Parameter Definitions

  • Active Lines Per Frame (ALPF)—Defines the number of lines in a Frame containing displayable data: ALPF is a subset of the TLPF.
  • Active Pixels Per Line (APPL)—Defines the number of pixel clocks in a line containing displayable data: APPL is a subset of the TPPL
  • Horizontal Back Porch Blanking (HBP)—Number of blank pixel clocks after Horizontal Sync but before the first active pixel. Note: HBP times are reference to the leading (active) edge of the respective sync signal
  • Horizontal Front Porch Blanking (HFP)—Number of blank pixel clocks after the last active pixel but before Horizontal Sync.
  • Horizontal Sync (HS)—Timing reference point that defines the start of each horizontal interval (line). The absolute reference point is defined by the “active” edge of the HS signal. The “active” edge (either rising or falling edge as defined by the source) is the reference from which all Horizontal Blanking parameters are measured.
  • Total Lines Per Frame (TLPF)—Defines the Vertical Period (or Frame Time) in lines: TLPF = Total number of lines per frame (active and inactive).
  • Total Pixel Per Line (TPPL)—Defines the Horizontal Line Period in pixel clocks: TPPL = Total number of pixel clocks per line (active and inactive).
  • Vertical Back Porch Blanking (VBP)—Number of blank lines after Vertical Sync but before the first active line.
  • Vertical Front Porch Blanking (VFP)—Number of blank lines after the last active line but before Vertical Sync.
  • Vertical Sync (VS)—Timing reference point that defines the start of the vertical interval (frame). The absolute reference point is defined by the “active” edge of the VS signal. The “active” edge (either rising or falling edge as defined by the source) is the reference from which all Vertical Blanking parameters are measured.
GUID-34F519AC-F4EF-44A7-9D86-6A28599808EC-low.gif Figure 11-1 Timing Parameter Diagram