DLPS223A December   2021  – February 2023 DLPC4430

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements
    7. 6.7  Test and Reset Timing Requirements
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  Port 1 Input Pixel Timing Requirements
    10. 6.10 Port 3 Input Pixel Interface (via GPIO) Timing Requirements
    11. 6.11 DMD LVDS Interface Timing Requirements
    12. 6.12 Synchronous Serial Port (SSP) Interface Timing Requirements
    13. 6.13 Programmable Output Clocks Switching Characteristics
    14. 6.14 Synchronous Serial Port Interface (SSP) Switching Characteristics
    15. 6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 System Reset Operation
        1. 7.3.1.1 Power-Up Reset Operation
        2. 7.3.1.2 System Reset Operation
      2. 7.3.2 Spread Spectrum Clock Generator Support
      3. 7.3.3 GPIO Interface
      4. 7.3.4 Source Input Blanking
      5. 7.3.5 Video Graphics Processing Delay
      6. 7.3.6 Program Memory Flash/SRAM Interface
      7. 7.3.7 Calibration and Debug Support
      8. 7.3.8 Board Level Test Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Regulations
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC4430 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.15V System Power
      3. 9.4.3 1.8V System Power
      4. 9.4.4 3.3V System Power
      5. 9.4.5 Power Good (PWRGOOD) Support
      6. 9.4.6 5V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal DLPC4430 Power
      2. 10.1.2 PCB Layout Guidelines for Auto-Lock Performance
      3. 10.1.3 DMD Interface Considerations
      4. 10.1.4 Layout Example
      5. 10.1.5 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Video Timing Parameter Definitions
      2. 11.2.2 Device Nomenclature
      3. 11.2.3 Device Markings
        1. 11.2.3.1 Device Marking
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1.3 DMD Interface Considerations

High speed interface waveform quality and timing on the DLPC4430 controller (that is, the LVDS DMD Interface) is dependent on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus ensuring positive timing margin requires attention to many factors.

As an example, DMD Interface system timing margin can be calculated as follows:

  • Setup Margin = (DLPC4430 output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)
  • Hold-time Margin = (DLPC4430 output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)

Where PCB SI degradation is signal integrity degradation due to PCB effects, which include simultaneously switching output (SSO) noise, cross-talk and inter-symbol interference (ISI) noise. The controller I/O timing parameters as well as DMD I/O timing parameters can be easily found in their corresponding data sheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI degradation is not so straight forward.

In an attempt to minimize the signal integrity analysis, the following PCB design guidelines are provided as a reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these recommendations may also work, but have to be confirmed with PCB signal integrity analysis or lab measurements

PDB Design:

● Configuration Asymmetric Dual Stripline
● Etch Thickness 1.0 oz copper (1.2 mil)
● Flex Etch Thickness 0.5 oz copper (0.6 mil)
● Single Ended Signal Impedance 50 ohms (+/– 10%)
● Differential Signal Impedance 100 ohms differential (+/– 10%)

PCB Stackup:

● Reference plane 1 is assumed to be a ground plane for proper return path
● Reference plane 2 is assumed to be the I/O power plane or ground
● Dielectric FR4, (Er): 4.2 (nominal)
● Signal trace distance to reference plane 1 (H1) 5.0 mil (nominal)
● Signal trace distance to reference plane 2 (H2) 34.2 mil (nominal)
GUID-E013DABB-BA3E-4001-8E31-9AA31AA3BBD3-low.jpg Figure 10-2 PCB Stackup Geometries
Table 10-1 General PCB Routing (Applies to All Corresponding PCB Signals)
PARAMETER APPLICATION SINGLE-ENDED SIGNAL DIFFERENTIAL PAIRS UNIT
Line width (W)(1) Escape Routing in Ball Field 4 (0.1) 4 (0.1) mil (mm)
PCB Etch Data or Control 7 (0.18) 4.25 (0.11) mil (mm)
PCB Etch Clocks 7 (0.18) 4.25 (0.11) mil (mm)
Minimum Line spacing to other signals (S) Escape Routing in Ball Field 4 (0.1) 4 (0.1) mil (mm)
PCB Etch Data or Control 10 (0.25) 20 (0.51) mil (mm)
PCB Etch Clocks 20 (0.51) 20 (0.51) mil (mm)
(1) Line width is expected to be adjusted to achieve impedance requirements.
Table 10-2 DMD I/F, PCB Interconnect Length Matching Requirements
SIGNAL GROUP LENGTH MATCHING
I/F SIGNAL GROUP REFERENCE SIGNAL MAX MISMATCH UNIT
DMD (LVDS) SCA_P,SCA_N, DDA_P(15:0), DDA_N(15:0) DCKA_P, DCKA_N +/-150 (+/–3.81) mil (mm)
DMD (LVDS) SCB_P,SCB_N, DDB_P(15:0), DDB_N(15:0) DCKB_P, DCKB_N +/-150 (+/–3.81) mil (mm)

Number of layer changes:

  • Single ended signals: Minimize
  • Differential signals: Individual differential pairs can be routed on different layers but the signals of a given pair typically does not change layers.

Termination requirements:

  • DMD Interface—None, the DMD receiver is differentially terminated to 100 ohms internally

    Connector (DMD-LVDS I/F bus only)—High Speed Connectors that meet the following requirements must be used:

    ● Differential Crosstalk <5 %
    ● Differential Impedance 75 ohms–125 ohms

Routing requirements for right angle connectors:

When using right angle connectors, P-N pairs have to be routed in same row to minimize delay mismatch and propagation delay difference for each row has to be accounted for on associated PCB etch lengths.