DLPS223 Data sheet

DLPS223A December 2021 – February 2023 DLPC4430

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

ZPC|516
- MPBGAJ0

Thermal pad, mechanical data (Package|Pins)

Orderable Information

dlps223a_oa

6.9 Port 1 Input Pixel Timing Requirements

		TEST CONDITIONS	MIN	MAX	UNIT
f_clock	Clock frequency, P_CLK1, P_CLK2, P_CLK3 (30-bit bus)		12	175	MHz
f_clock	Clock frequency, P_CLK1, P_CLK2, P_CLK3 (60-bit bus)		12	141	MHz
t_C	Cycle Time, P_CLK1, P_CLK2, P_CLK3		5.714	83.33	ns
t_W(H)	Pulse Duration, high	50% to 50% reference points (signal)	2.3		ns
t_W(L)	Pulse Duration, low	50% to 50% reference points (signal)	2.3		ns
t_jp	Clock period jitter, P_CLK1, P_CLK2, P_CLK3	Max ƒ_clock		See ⁽²⁾	ps
t_t	Transition time, t_t=t_f/t_r, P_CLK1, P_CLK2, P_CLK3	20% to 80% reference points (signal)	0.6	2.0	ns
t_t	Transition time, t_t=t_f/t_r, P1_A(9-0), P1_B(9-0), P1_C(9-0), P1_HSYNC, P1_VSYNC, P1_DATAEN	20% to 80% reference points (signal)	0.6	3.0	ns
t_t	Transition time, t_t=t_f/t_r, ALF_HSYNC, ALF_VSYNC, ALF_CSYNC⁽¹⁾	20% to 80% reference points (signal)	0.6	3.0	ns
SETUP AND HOLD TIMES
t_su	Setup time, P1_A(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P1_A(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_su	Setup time, P1_B(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P1_B(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_su	Setup time, P1_C(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P1_C(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_su	Setup time, P1_VSYNC, valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P1_VSYNC valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_su	Setup time, P1_HSYNC, valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P1_HSYNC valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_su	Setup time, P2_A(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P2_A(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_su	Setup time, P2_B(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P2_B(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_su	Setup time, P2_C(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P2_C(9-0), valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_su	Setup time, P2_VSYNC, valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P2_VSYNC valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_su	Setup time, P2_HSYNC, valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P2_HSYNC valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_su	Setup time, P_DATAEN1, valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P_DATAEN1 valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_su	Setup time, P_DATAEN2, valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_h	Hold time, P_DATAEN2 valid before P_CLK1↑↓, P_CLK2↑↓, or P_CLK3↑↓		0.8		ns
t_w(A)	VSYNC Active Pulse Width		1		Video Line
t_w(A)	HSYNC Active Pulse Width		16		Pixel Clocks

(1) ALF_CSYNC, ALF_VSYNC and ALF_HSYNC are Asynchronous signals.

(2) For frequencies (fclock) less than 175 MHZ, use following formula to obtain the jitter: Max Clock Jitter = +/- [ (1/ƒ_clock) – 5414 ps]