DLPS223A December   2021  – February 2023 DLPC4430

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements
    7. 6.7  Test and Reset Timing Requirements
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  Port 1 Input Pixel Timing Requirements
    10. 6.10 Port 3 Input Pixel Interface (via GPIO) Timing Requirements
    11. 6.11 DMD LVDS Interface Timing Requirements
    12. 6.12 Synchronous Serial Port (SSP) Interface Timing Requirements
    13. 6.13 Programmable Output Clocks Switching Characteristics
    14. 6.14 Synchronous Serial Port Interface (SSP) Switching Characteristics
    15. 6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 System Reset Operation
        1. 7.3.1.1 Power-Up Reset Operation
        2. 7.3.1.2 System Reset Operation
      2. 7.3.2 Spread Spectrum Clock Generator Support
      3. 7.3.3 GPIO Interface
      4. 7.3.4 Source Input Blanking
      5. 7.3.5 Video Graphics Processing Delay
      6. 7.3.6 Program Memory Flash/SRAM Interface
      7. 7.3.7 Calibration and Debug Support
      8. 7.3.8 Board Level Test Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Regulations
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC4430 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.15V System Power
      3. 9.4.3 1.8V System Power
      4. 9.4.4 3.3V System Power
      5. 9.4.5 Power Good (PWRGOOD) Support
      6. 9.4.6 5V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal DLPC4430 Power
      2. 10.1.2 PCB Layout Guidelines for Auto-Lock Performance
      3. 10.1.3 DMD Interface Considerations
      4. 10.1.4 Layout Example
      5. 10.1.5 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Video Timing Parameter Definitions
      2. 11.2.2 Device Nomenclature
      3. 11.2.3 Device Markings
        1. 11.2.3.1 Device Marking
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Calibration and Debug Support

The DLPC4430 controller contains a test point output port, TSTPT_(7:0), which provides selected system calibration support as well as ASIC debug support. These test points are inputs while reset is applied and switch to outputs when reset is released. The state of these signals is sampled upon the release of system reset and the captured value configures the test mode until the next time reset is applied. Each test point includes an internal pull-down resistor and thus external pull-ups are used to modify the default test configuration. The default configuration (x00) corresponds to the TSTPT_(7:0) outputs being driven low for reduce switching activity during normal operation. For maximum flexibility, an option to jumper to an external pull-up is recommended for TSTPT_(3:0). Note that adding pull-up to TSTPT_(7:4) may have adverse affects for normal operation and are not recommended. Note that these external pull-ups are only sampled upon a zero to one transition on POSENSE and thus changing their configuration after reset has been released does not have any effect until the next time reset is asserted and released. #GUID-BFB30140-58D2-409D-B692-F840F57A7AF3/GUID-80EF0662-23D8-4613-8DD4-7371900F786B defines the test mode selection for 3 of the 16 programmable scenarios defined by TSTPT_(3:0):

Table 7-4 Test Mode Selection
No Switching Activity System Calibration ARM Debug Signal Set
TSTPT(3:0) Capture Value x0 x8 x1
TSTPT(0) 0 Vertical Sync ARM9_Debug (0)
TSTPT(1) 0 Delayed CW Index ARM9_Debug (1)
TSTPT(2) 0 Sequence Index ARM9_Debug (2)
TSTPT(3) 0 CW Spoke Test Pt ARM9_Debug (3)
TSTPT(4) 0 CW Revolution Test Pt ARM9_Debug (4)
TSTPT(5) 0 Reset Seq. Aux Bit 0 ARM9_Debug (5)
TSTPT(6) 0 Reset Seq. Aux Bit 1 ARM9_Debug (6)
TSTPT(7) 0 Reset Seq. Aux Bit 2 ARM9_Debug (7)