DLPS168C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Power Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAX(1)UNIT
V(VDD115)1.15-V PowerMaximum current at VDD115 = 1.2 V5640mA
V(VDD115_PLLMA) (Core)1.15-V Digital Power
MCG-A PLL
(Master Clock Generator)		Maximum current at VDD115_PLLMA = 1.2 V6mA
V(VDD115_PLLMB) (Core)1.15-V Digital Power
MCG-B PLL
(Master Clock Generator)		Maximum current at VDD115_PLLMB = 1.2 V6mA
V(VDD115_PLLS) (Core)1.15-V Analog Power
SCG Doubler PLL		Maximum current at VDD115_PLLS = 1.2 V3mA
V(VAD115_FPD) (Core) (2)1.15-V Analog Power
FPD		Maximum current at VAD115_FPD = 1.2 V
Ports A and B Active, Port C inactive		99mA
V(VAD115_VX1) (Core) (2)1.15-V Analog Power
VX1		Maximum current at VAD115_VX1 = 1.2 V
8 Lanes, with total BW = 3.0Gbps)		400mA
V(VAD115_HSSI) (Core)1.15-V Digital Power
HSSI		Maximum current at VDD115_HSSI = 1.2 V
Both ports active		462mA
V(VAD115_HSSI0_PLL) (Core)1.15-V Digital Power
HSSI0 PLL		Maximum current at VDD115_HSSI0_PLL = 1.2 V
Both ports active		1mA
V(VAD115_HSSI1_PLL) (Core)1.15-V Digital Power
HSSI1 PLL		Maximum current at VDD115_HSSI1_PLL = 1.2 V
Both ports active		1mA
V(VDD121_SCS) (Core)1.21V Digital Power
SCS DRAM		Maximum current at VDD121_SCS = 1.30 V334mA
V(VAD18_PLLMA) (Core)1.8-V Analog Power
MCG-A PLL
(Master Clock Generator)		Maximum current at VAD18_PLLMA = 1.89 V10mA
V(VAD18_PLLMB) (Core)1.8-V Analog Power
MCG-B PLL
(Master Clock Generator)		Maximum current at VAD18_PLLMB = 1.89 V10mA
V(VAD18_VX1) (I/O) (2)1.8-V Analog Power
VX1 Interface		Maximum current at VAD18_VX1 = 1.89 V
8 Lanes, with total BW = 3.0Gbps		41mA
V(VDD18_SCS) (Core)1.8-V Digital Power
SCS DRAM		Maximum current at VDD18_SCS = 1.89 V327mA
V(VDD18_LVDS) (I/O)1.8-V Analog Power
DMD LS Interface		Maximum current at VDD18_LVDS = 1.89 V31mA
V(VDD33) (I/O)3.3-V Digital Power - (All 3.3-V I/O without dedicated 3.3-V supply - e.g. GPIO)Maximum current at VDD33 = 3.3456 V28mA
V(VAD33_OSCA) (I/O)3.3-V Analog Power
Crystal/OSCA Interface		Maximum current at VDD33_OSCA = 3.3456 V5mA
V(VAD33_OSCB) (I/O)3.3-V Analog Power
Crystal-OSCB Interface		Maximum current at VDD33_OSCB =3.3456 V5mA
V(VDD33_FPD) (I/O) (2)3.3-V Digital Power
FPD interface		Maximum current at VDD33_FPD = 3.3456 V
Ports A and B Active, Port C inactive		102mA
V(VAD33_USB) (I/O)3.3-V Analog Power
USB Interface		Maximum current at VDD33_USB =3.3456 V78mA
V(VDD33_HSSI) (I/O)3.3-V Digital Power
DMD HSSI Interface		Maximum current at VDD33_HSSI = 3.3456 V
Both ports active, with total BW = 3.0Gbps		194mA
(1) Vendor estimate for worst case power PVT condition = corner process, high voltage, high temperature (115°C junction).
(2) The V-by-One interface and FPD-Link receivers are never intended to be simultaneously enabled . Always disable one of these interfaces.