DLPS271 April   2024 DLPC7530

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  DMD HSSI Electrical Characteristics
    8. 5.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 5.9  V-by-One Interface Electrical Characteristics
    10. 5.10 FPD-Link LVDS Electrical Characteristics
    11. 5.11 USB Electrical Characteristics
    12. 5.12 System Oscillator Timing Requirements
    13. 5.13 Power Supply and Reset Timing Requirements
    14. 5.14 DMD HSSI Timing Requirements
    15. 5.15 DMD Low-Speed LVDS Timing Requirements
    16. 5.16 V-by-One Interface General Timing Requirements
    17. 5.17 FPD-Link Interface General Timing Requirements
    18. 5.18 Parallel Interface General Timing Requirements
    19. 5.19 Source Frame Timing Requirements
    20. 5.20 Synchronous Serial Port Interface Timing Requirements
    21. 5.21 Controller and Target I2C Interface Timing Requirements
    22. 5.22 Programmable Output Clock Timing Requirements
    23. 5.23 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    24. 5.24 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    25. 5.25 Multi-Trace ETM Interface Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Sources
      2. 6.3.2 Processing Delays
      3. 6.3.3 Parallel Interface
      4. 6.3.4 FPD-Link Interface
      5. 6.3.5 V-by-One Interface
      6. 6.3.6 DMD (HSSI) Interface
      7. 6.3.7 Program Memory Flash Interface
      8. 6.3.8 GPIO Supported Functionality
      9. 6.3.9 Debug Support
    4. 6.4 Device Operational Modes
      1. 6.4.1 Standby Mode
      2. 6.4.2 Active Mode
        1. 6.4.2.1 Normal Configuration
        2. 6.4.2.2 Low Latency Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
  9. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General Layout Guidelines
      2. 9.1.2  Power Supply Layout Guidelines
      3. 9.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4  Layout Guideline for DLPC7530 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5  V-by-One Interface Layout Considerations
      6. 9.1.6  FPD-Link Interface Layout Considerations
      7. 9.1.7  USB Interface Layout Considerations
      8. 9.1.8  DMD Interface Layout Considerations
      9. 9.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 9.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1. 10.6.1 Video Timing Parameter Definitions
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     92

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.13 Power Supply and Reset Timing Requirements

PARAMETER MIN MAX UNIT
tRAMP-UP Power supply ramp-up time(1) (Figure 5-5) Power supply ramp for each supply
Ramp-up time: TOV × 10% to TOV × 90%
TOV = Typical Operational Voltage		 0.01 10 ms
tRAMP-UP-TOTAL Total power supply ramp-up time(1) Total time within which the 1.15V, 1.8V, 1.21V, and 3.3V supplies must complete their ramp-up from the start of the 1.15V ramp-up.
Ramp-up time: TOV × 10% to TOV × 90%
TOV = typical operational voltage		 100 ms
tRAMP-DOWN Power supply ramp-down time(1) (Figure 5-5, Figure 5-6) Power supply ramp for each supply
Ramp-down time: TOV × 90% to TOV × 10%
TOV = typical operational voltage		 0 100 ms
tRAMP-DOWN-TOTAL Total power supply ramp-down time(1) Total time within which the 1.15V, 1.8V, 1.21V, and 3.3V supplies must complete their ramp-down from the start of the 3.3V ramp-up.
Ramp-down time: TOV × 90% to TOV × 10%
TOV = typical operational voltage		 100 ms
tRUSD18 1.8V supply ramp-up start delay(2) (Figure 5-6) Delay from 1.15V supply ramp start to 1.8V supply ramp start See(3) ms
tRUSD33 3.3V supply ramp-up start delay (2) (Figure 5-6) Delay from 1.15V supply ramp start to 3.3V supply ramp start 10 50 ms
tRUSD12 1.21V supply ramp-up start delay, (2) (Figure 5-6) Delay from 1.8V supply ramp start to 1.21V supply ramp start See(4) ms
tRDSD18 1.8V supply ramp-down start delay, (2) (Figure 5-6) Delay from 1.21V supply ramp start to 1.8V supply ramp start See(5) ms
tRDSD115 1.15V supply ramp-down start delay, (2) (Figure 5-6) Delay from 3.3V supply ramp start to 1.15V supply ramp start See(8)
tEW Early warning time (Figure 5-8) PWRGOOD goes inactive low (as an early warning) prior to any power supply voltage going below the controller specification 500 µs
tPH Power hold time (Figure 5-8) POSENSE remains active after PWRGOOD is disabled. 500(9) µs
tw1 Pulse duration, in-active low, PWRGOOD (Figure 5-7) PWRGOOD inactive time while POSENSE is active
50% to 50% reference points (signal)		 4 1000(6) µs
tt1 Transition time, PWRGOOD
tt1 = tƒ1 and tr1
(Figure 5-7)		 Rise and Fall time for PWRGOOD
20% to 80% reference points (signal)		 625 µs
tw2 Pulse duration, in-active low, POSENSE (Figure 5-8) POSENCE inactive time while PWRGOOD is inactive
50% to 50% reference points (signal)		 100 ms
tt2 Transition time, POSENSE
tt1 = tƒ1 and tr1
(Figure 5-8)		 Rise and Fall time for POSENSE (7)
20% to 80% reference points (signal)		 25 µs
tPSD PWRGOOD start delay (Figure 5-7) Time after rising edge of POSENSE before PWRGOOD effects DLPC7530 operation 51.5 60 ms
tPROJ_ON PROJ_ON fall time delay to PWRGOOD (Figure 5-8) Fall Delay
PROJ_ON 80% to PWRGOOD 80% fall time start		 10 ms
tREFCLKA Time to stable REFCLKA (Figure 5-7) Time to stable REFLCKA before POSENSE See(10)
(1) It is assumed that all 1.15V supplies come from the same source, although some can have additional filtering before entering the DLPC7530. As such, it is expected these supplies to ramp together (aside from differences caused by filtering). This same expectation is true for the 1.21V, 1.8V, and 3.3V supplies.
(2) The DLPC7530 has specific power supply sequencing requirements, listed below, that include the timings specified in this table.
  1. Power Up Order:
    1. 1.15V (Core, Analog) » 1.8V (I/O, SCS) » 1.21V (SCS)
    2. 1.15V (Core, Analog) » 3.3V (I/O
  2. Power Down Order:
    1. 3.3V (I/O) » 1.15V (Core, Analog)
    2. 1.21V (SCS) » 1.8V (I/O, SCS) » 1.15V (Core, Analog)
(3) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.15V power supply ramp-up is started, and the second event is when the 1.15V supply ramp-up reaches 80% of TOV (at which point the 1.8V supply can start its ramp-up). Because the occurrence of the second event depends on the specific design of the 1.15V power supply, the designer must determine the specific delay time.
(4) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.8V power supply ramp-up is started, and the second event is when the 1.8V supply ramp-up reaches 80% of TOV (at which point the 1.21V supply can start its ramp-up). Because the occurrence of the second event depends on the specific design of the 1.8V power supply, the designer must determine the specific delay time.
(5) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.21V power supply ramp-down is started, and the second event is when the 1.21V supply ramp-down reaches 20% of TOV (at which point the 1.8V supply can start its ramp-down). Because the occurrence of the second event depends on the specific design of the 1.21V power supply, the designer must determine the specific delay time. The intent of this delay time is to determine that the voltage level of the 1.8V supply never falls lower than the voltage level of the 1.21V supply during the ramp-down until the 1.2V supply is below 300 mV.
(6) This max value is only applicable if the 1.8V power remains ON while PWRGOOD is inactive. Otherwise, there is no maximum limit.
(7) As long as noise on this signal is below the hysteresis threshold
(8) This delay requirement parameter is defined as the time between two events. The first event is the point where the 3.3V power supply ramp-down is started, and the second event is when the 3.3V supply ramp-down and 1.8V supply ramp down reaches 10% of TOV (at which point the 1.15V supply can start its ramp-down). Because the occurrence of the second event depends on the specific design of the 3.3V and 1.8V power supply, the designer must determine the specific delay time.
(9) If PROJ_ON is used for power down then Power Hold Time (tPH) is not required.
(10) This delay requirement parameter is defined by design of RECLKA oscillator. Stable clock must be provided before releasing POSENSE.

DLPC7530 Power Supply Ramp Time Figure 5-5 Power Supply Ramp Time
DLPC7530 Power Supply Ramp Sequencing Profiles Figure 5-6 Power Supply Ramp Sequencing Profiles
DLPC7530 Power Up Timing Figure 5-7 Power Up Timing
DLPC7530 Power Down Timing—Normal Figure 5-8 Power Down Timing—Normal
DLPC7530 Power Down Timing—Fault Figure 5-9 Power Down Timing—Fault