DLPS271 April   2024 DLPC7530

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  DMD HSSI Electrical Characteristics
    8. 5.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 5.9  V-by-One Interface Electrical Characteristics
    10. 5.10 FPD-Link LVDS Electrical Characteristics
    11. 5.11 USB Electrical Characteristics
    12. 5.12 System Oscillator Timing Requirements
    13. 5.13 Power Supply and Reset Timing Requirements
    14. 5.14 DMD HSSI Timing Requirements
    15. 5.15 DMD Low-Speed LVDS Timing Requirements
    16. 5.16 V-by-One Interface General Timing Requirements
    17. 5.17 FPD-Link Interface General Timing Requirements
    18. 5.18 Parallel Interface General Timing Requirements
    19. 5.19 Source Frame Timing Requirements
    20. 5.20 Synchronous Serial Port Interface Timing Requirements
    21. 5.21 Controller and Target I2C Interface Timing Requirements
    22. 5.22 Programmable Output Clock Timing Requirements
    23. 5.23 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    24. 5.24 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    25. 5.25 Multi-Trace ETM Interface Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Sources
      2. 6.3.2 Processing Delays
      3. 6.3.3 Parallel Interface
      4. 6.3.4 FPD-Link Interface
      5. 6.3.5 V-by-One Interface
      6. 6.3.6 DMD (HSSI) Interface
      7. 6.3.7 Program Memory Flash Interface
      8. 6.3.8 GPIO Supported Functionality
      9. 6.3.9 Debug Support
    4. 6.4 Device Operational Modes
      1. 6.4.1 Standby Mode
      2. 6.4.2 Active Mode
        1. 6.4.2.1 Normal Configuration
        2. 6.4.2.2 Low Latency Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
  9. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General Layout Guidelines
      2. 9.1.2  Power Supply Layout Guidelines
      3. 9.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4  Layout Guideline for DLPC7530 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5  V-by-One Interface Layout Considerations
      6. 9.1.6  FPD-Link Interface Layout Considerations
      7. 9.1.7  USB Interface Layout Considerations
      8. 9.1.8  DMD Interface Layout Considerations
      9. 9.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 9.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1. 10.6.1 Video Timing Parameter Definitions
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     92

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.7 Program Memory Flash Interface

The DLPC7530 provides three external program memory chip selects for devices to access the program memory interface. These are detailed in Table 6-20.

Table 6-20 Program Memory Interface Chip Selects
CHIP SELECT NAMECHIP SELECT USEDATA BUS WIDTHACCESS TIMEMAXIMUM SIZE SUPPORTED (1)
PM_CSZ_0Boot FLASH only - Required (2)16 bits< = 120ns256Mb
PM_CSZ_1Additional Peripheral Device (or additional FLASH) - Optional16 bits< = 120ns256Mb
PM_CSZ_2Additional Peripheral Device - Optional16 bits< = 120ns256Mb
(1) Using GPIO_47 as additional address bit
(2) Boot FLASH type supported is Standard NOR parallel FLASH, single or multi-bank.

FLASH access timing is software programmable with up to 31 wait states. Additional information about read and write wait state timing is provided in Table 6-21 and Figure 6-6.

Table 6-21 Program Memory Wait State Timing
PARAMETEREQUATION (1)
TWSR: Wait State Resolution6ns
Read Wait States
(Number of Read Wait States for each CSz read access)		ROUNDUP(MAX(TACC, TCE,TOE)/TWSR-N) (2)(3)
Write Wait States for TCSand TAS
(Time from CS/Address activation to WRZ assertion)		ROUNDUP(MAX(TCS+5ns, TAS+5ns)/TWSR-N) (2)
Write Wait States for TWP and TDS
(Time from WRZ assertion to WEZ de-assertion)		ROUNDUP(MAX(TWP+5ns, TDS+5ns)/TWSR-N) (2)
Write Wait States for TCHand TDH
(Time from CS/Address activation to WRZ assertion)		ROUNDUP(MAX(TCH+5ns, TDH+5ns)/TWSR-N) (2)
(1)
  1. TACC: Read Access Time (ADDR to DATA valid) – (address valid to DATA valid)
  2. TCE: Read Access Time (CSZ to DATA valid) – (chip select active to DATA valid)
  3. TOE: Read Access Time (OEZ to DATA valid) – (output enable active to DATA valid)
  4. TCS: CSZ Setup Time (Writes) – (chip select active before negedge(WEZ)
  5. TCS: Address Setup Time (Writes) – (address valid before negedge(WEZ)
  6. TAS: Address Setup Time (Writes) – (address valid before negedge(WEZ)
  7. TWP: Write Pulse Width (Writes) – (WEZ active low time)
  8. TDS: Data Setup Time (Writes) – (DATA valid before posedge(WEZ)
  9. TCH: CSZ Hold Time (Writes) – (CSZ held active after posedge(WEZ)
  10. TDH: Data Hold Time (Writes) – (DATA held valid after posedge(WEZ)
(2) Requires a minimum of at least 1 wait state
(3) Assumes a maximum single direction trace length of 90mm (3.5 inches)
DLPC7530 Program Memory Interface Timing DiagramFigure 6-6 Program Memory Interface Timing Diagram