DLPS271 April   2024 DLPC7530

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  DMD HSSI Electrical Characteristics
    8. 5.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 5.9  V-by-One Interface Electrical Characteristics
    10. 5.10 FPD-Link LVDS Electrical Characteristics
    11. 5.11 USB Electrical Characteristics
    12. 5.12 System Oscillator Timing Requirements
    13. 5.13 Power Supply and Reset Timing Requirements
    14. 5.14 DMD HSSI Timing Requirements
    15. 5.15 DMD Low-Speed LVDS Timing Requirements
    16. 5.16 V-by-One Interface General Timing Requirements
    17. 5.17 FPD-Link Interface General Timing Requirements
    18. 5.18 Parallel Interface General Timing Requirements
    19. 5.19 Source Frame Timing Requirements
    20. 5.20 Synchronous Serial Port Interface Timing Requirements
    21. 5.21 Controller and Target I2C Interface Timing Requirements
    22. 5.22 Programmable Output Clock Timing Requirements
    23. 5.23 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    24. 5.24 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    25. 5.25 Multi-Trace ETM Interface Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Sources
      2. 6.3.2 Processing Delays
      3. 6.3.3 Parallel Interface
      4. 6.3.4 FPD-Link Interface
      5. 6.3.5 V-by-One Interface
      6. 6.3.6 DMD (HSSI) Interface
      7. 6.3.7 Program Memory Flash Interface
      8. 6.3.8 GPIO Supported Functionality
      9. 6.3.9 Debug Support
    4. 6.4 Device Operational Modes
      1. 6.4.1 Standby Mode
      2. 6.4.2 Active Mode
        1. 6.4.2.1 Normal Configuration
        2. 6.4.2.2 Low Latency Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
  9. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General Layout Guidelines
      2. 9.1.2  Power Supply Layout Guidelines
      3. 9.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4  Layout Guideline for DLPC7530 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5  V-by-One Interface Layout Considerations
      6. 9.1.6  FPD-Link Interface Layout Considerations
      7. 9.1.7  USB Interface Layout Considerations
      8. 9.1.8  DMD Interface Layout Considerations
      9. 9.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 9.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1. 10.6.1 Video Timing Parameter Definitions
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     92

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TOLERANCE MIN NOM MAX UNIT
V(VDD115) (Core) 1.15V Power ± 4.35% tolerance 1.10 1.15 1.20 V
V(VDD115_PLLMA) (Core) 1.15V Digital Power - MCG-A PLL
(Controller Clock Generator)		 +4.35/–9.13% tolerance 1.045 1.15 1.20 V
V(VDD115_PLLMB) (Core) 1.15V Digital Power - MCG-B PLL
(Controller Clock Generator)		 +4.35/–9.13% tolerance 1.045 1.15 1.20 V
V(VDD115_PLLS) (Core) 1.15V Analog Power - SCG Doubler PLL +4.35/–9.13% tolerance 1.045 1.15 1.20 V
V(VAD115_FPD) (Core) 1.15V Analog Power - FPD +4.35/–9.13% tolerance 1.045 1.15 1.20 V
V(VAD115_VX1) (Core) 1.15V Analog Power - VX1 +4.35/–9.13% tolerance 1.045 1.15 1.20 V
V(VAD115_HSSI) (Core) 1.15V Analog Power - HSSI +4.35/–9.13% tolerance 1.045 1.15 1.20 V
ΔV(VAD115_HSSI) (Core) pk-pkVAD115_HSSI supply noise @ 10MHz (sine) 20 mV
V(VAD115_HSSI0_PLL) (Core) 1.15V Analog Power - HSSI0 PLL +4.35/–9.13% tolerance 1.045 1.15 1.20 V
ΔV(VAD115_HSSI0_PLL) (Core) pk-pkVAD115_HSSI0_PLL supply noise @ 10MHz (sine) 20 mV
V(VAD115_HSSI1_PLL) (Core) 1.15V Analog Power - HSSI1 PLL +4.35/–9.13% tolerance 1.045 1.15 1.20 V
ΔV(VAD115_HSSI1_PLL) (Core) pk-pkVAD115_HSSI1_PLL supply noise @ 10MHz (sine) 20 mV
V(VDD121_SCS) (Core) 1.21V Digital Power - SCS DRAM +7.43/–4.95% tolerance 1.15 1.21 1.30 V
V(VAD18_PLLMA) (Core) 1.8V Analog Power - MCG-A PLL
(Controller Clock Generator)		 ±5.0% tolerance 1.71 1.80 1.89 V
V(VAD18_PLLMB) (Core) 1.8V Analog Power - MCG-B PLL
(Controller Clock Generator)		 ±5.0% tolerance 1.71 1.80 1.89 V
V(VAD18_VX1) (I/O) 1.8V Analog Power - VX1 Interface ±5.0% tolerance 1.71 1.80 1.89 V
V(VDD18_SCS) (Core) 1.8V Digital Power - SCS DRAM ±5.0% tolerance 1.71 1.80 1.89 V
V(VDD18_LVDS) (I/O) 1.8V Analog Power - DMD LS Interface ±5.0% tolerance 1.71 1.80 1.89 V
V(VDD33) (I/O) 3.3V Digital Power - (All 3.3V I/O without dedicated 3.3V supply - for example, GPIO) ±5.0% tolerance 3.135 3.3 3.465 V
V(VAD33_OSCA) (I/O) 3.3V Analog Power - Crystal-OSCA Interface ±5.0% tolerance 3.135 3.3 3.465 V
V(VAD33_OSCB) (I/O) 3.3V Analog Power - Crystal-OSCB Interface ±5.0% tolerance 3.135 3.3 3.465 V
V(VDD33_FPD) (I/O) 3.3V Digital Power - FPD interface ±5.0% tolerance 3.135 3.3 3.465 V
V(VAD33_USB) (I/O) 3.3V Analog Power - USB Interface ±5.0% tolerance 3.135 3.3 3.465 V
V(VDD33_HSSI) (I/O) 3.3V Digital Power - DMD HSSI Interface ±5.0% tolerance 3.135 3.3 3.465 V
ΔV(VDD33_HSSI) (I/O) pk-pkVDD33_HSSI supply noise @ 10MHz (sine) 60 mV
GENERAL
TJ Operating junction temperature 0 115 °C
TC Operating case temperature 0 108 °C
TA Operating ambient temperature (1)(2) 0 55 °C
(1) The operating ambient temperature range values were determined based on the board design parameters described in Section 9.1.1, rather than using a JEDEC JESD51 standard test card and environment, along with min and max estimated power dissipation across process, voltage, and temperature. Ambient thermal conditions, which impact RθJA, vary by application. Thus, maximum operating ambient temperature varies by application.
  1. Ta_min = Tj_min – (Pd_min × RθJA) = 0°C – (host_min_valueW × host_value°C/W) = –host_calculated_value°C
  2. Ta_max = Tj_max – (Pd_max × RθJA) = +115°C – (host_max_valueW × host_value°C/W) = +host_calculated_value°C
(2) Operating ambient temperature is dependent on system thermal design. Operating case temperature cannot exceed its specified range across ambient temperature conditions.