DLPS271 April   2024 DLPC7530

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  DMD HSSI Electrical Characteristics
    8. 5.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 5.9  V-by-One Interface Electrical Characteristics
    10. 5.10 FPD-Link LVDS Electrical Characteristics
    11. 5.11 USB Electrical Characteristics
    12. 5.12 System Oscillator Timing Requirements
    13. 5.13 Power Supply and Reset Timing Requirements
    14. 5.14 DMD HSSI Timing Requirements
    15. 5.15 DMD Low-Speed LVDS Timing Requirements
    16. 5.16 V-by-One Interface General Timing Requirements
    17. 5.17 FPD-Link Interface General Timing Requirements
    18. 5.18 Parallel Interface General Timing Requirements
    19. 5.19 Source Frame Timing Requirements
    20. 5.20 Synchronous Serial Port Interface Timing Requirements
    21. 5.21 Controller and Target I2C Interface Timing Requirements
    22. 5.22 Programmable Output Clock Timing Requirements
    23. 5.23 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    24. 5.24 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    25. 5.25 Multi-Trace ETM Interface Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Sources
      2. 6.3.2 Processing Delays
      3. 6.3.3 Parallel Interface
      4. 6.3.4 FPD-Link Interface
      5. 6.3.5 V-by-One Interface
      6. 6.3.6 DMD (HSSI) Interface
      7. 6.3.7 Program Memory Flash Interface
      8. 6.3.8 GPIO Supported Functionality
      9. 6.3.9 Debug Support
    4. 6.4 Device Operational Modes
      1. 6.4.1 Standby Mode
      2. 6.4.2 Active Mode
        1. 6.4.2.1 Normal Configuration
        2. 6.4.2.2 Low Latency Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
  9. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General Layout Guidelines
      2. 9.1.2  Power Supply Layout Guidelines
      3. 9.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4  Layout Guideline for DLPC7530 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5  V-by-One Interface Layout Considerations
      6. 9.1.6  FPD-Link Interface Layout Considerations
      7. 9.1.7  USB Interface Layout Considerations
      8. 9.1.8  DMD Interface Layout Considerations
      9. 9.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 9.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1. 10.6.1 Video Timing Parameter Definitions
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     92

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.5 V-by-One Interface

The DLPC7530 controller supports a single 8 lane V-by-One port that can be configured for 1, 2, 4, or 8 lane use. This interface supports limited lane remapping, which is shown in Table 6-8 . Intra-lane remapping (that is, swapping P with N) is not supported.

Table 6-8 V-by-One Interface Lane Remapping Options
V-BY-ONE PORT PHYSICAL LANES (1)
CONFIGURATION (1) # OF LANES LANE 7 LANE 6 LANE 5 LANE 4 LANE 3 LANE 2 LANE 1 LANE 0
1 8 7 6 5 4 3 2 1 0
2 8 1 0 2 3 4 5 6 7
(1) There are two controller lane mapping options, with the option to use fewer than the full eight lanes for each of these.

Independent from the remapping of the physical V-by-One interface, the DLPC7530 supports a number of data mappings onto the actual physical interface as specified by the standard. V-by-One sources must match at least one of these mappings. These are shown in Table 6-9, Table 6-10, Table 6-11, Table 6-12, Table 6-13, Table 6-14, Table 6-15, Table 6-16, Table 6-17, and Table 6-18.

Table 6-9 V-by-One Data Mapping for 36bpp/30bpp RGB/YCbCr 4:4:4
V-by-One DATA MAP MODE 0
V-by-One INPUT DATA BIT 36bpp RGB/YCbCr 4:4:4 (1) 30bpp RGB/YCbCr 4:4:4 MAPPER OUTPUT
D[0] R/Cr[4] R/Cr[2] B(2)
D[1] R/Cr[5] R/Cr[3] B(3)
D[2] R/Cr[6] R/Cr[4] B(4)
D[3] R/Cr[7] R/Cr(5] B(5)
D[4] R/Cr[8] R/Cr[6] B(6)
D[5] R/Cr[9] R/Cr[7] B(7)
D[6] R/Cr[10] R/Cr[8] B(8)
D[7] R/Cr[11] R/Cr[9] B(9)
D[8] G/Y[4] G/Y[2] A(2)
D[9] G/Y[5] G/Y[3] A(3)
D[10] G/Y[6] G/Y[4] A(4)
D[11] G/Y[7] G/Y[5] A(5)
D[12] G/Y[8] G/Y[6] A(6)
D[13] G/Y[9] G/Y[7] A(7)
D[14] G/Y[10] G/Y[8] A(8)
D[15] G/Y[11] G/Y[9] A(9)
D[16] B/Cb[4] B/Cb[2] C(2)
D[17] B/Cb[5] B/Cb[3] C(3)
D[18] B/Cb[6] B/Cb[4] C(4)
D[19] B/Cb[7] B/Cb[5] C(5)
D[20] B/Cb[8] B/Cb[6] C(6)
D[21] B/Cb[9] B/Cb[7] C(7)
D[22] B/Cb[10] B/Cb[8] C(8)
D[23] B/Cb[11] B/Cb[9] C(9)
D[24] - - -
D[25] - - -
D[26] B/Cb[2] B/Cb[1] C[0]
D[27] B/Cb[3] B/Cb[0] C[1]
D[28] G/Y[2] G/Y[1] A[0]
D[29] G/Y[3] G/Y[0] A[1]
D[30] R/Cr[2] R/Cr[1] B[0]
D[31] R/Cr[3] R/Cr[0] B[1]
(1) For 36-bit inputs, the 12 bits per color truncate to 10-bits per color with the two least significant bits per color being discarded.
Table 6-10 V-by-One Data Mapping for 27bpp RGB/YCbCr 4:4:4
V-by-One DATA MAP MODE 1
V-by-One INPUT DATA BIT 27bpp RGB/YCbCr 4:4:4 (1) MAPPER OUTPUT
D[0] R/Cr[1] B(2)
D[1] R/Cr[2] B(3)
D[2] R/Cr[3] B(4)
D[3] R/Cr[4] B(5)
D[4] R/Cr[5] B(6)
D[5] R/Cr[6] B(7)
D[6] R/Cr[7] B(8)
D[7] R/Cr[8] B(9)
D[8] G/Y[1] A(2)
D[9] G/Y[2] A(3)
D[10] G/Y[3] A(4)
D[11] G/Y[4] A(5)
D[12] G/Y[5] A(6)
D[13] G/Y[6] A(7)
D[14] G/Y[7] A(8)
D[15] G/Y[8] A(9)
D[16] B/Cb[1] C(2)
D[17] B/Cb[2] C(3)
D[18] B/Cb[3] C(4)
D[19] B/Cb[4] C(5)
D[20] B/Cb[5] C(6)
D[21] B/Cb[6] C(7)
D[22] B/Cb[7] C(8)
D[23] B/Cb[8] C(9)
D[24] - -
D[25] - -
'0' — C[0]
D[27] B/Cb[0] C[1]
'0' — A[0]
D[29] G/Y[0] A[1]
'0' — B[0]
D[31] R/Cr[0] B[1]
(1) For 27-bit inputs, the 9 bits for each color shifts up one bit, and the least significant bit of each color is set to '0'.
Table 6-11 V-by-One Data Mapping for 24bpp RGB/YCbCr 4:4:4
V-by-One DATA MAP MODE 2
V-by-One INPUT DATA BIT 24bpp RGB/YCbCr 4:4:4 (1) MAPPER OUTPUT
D[0] R/Cr[0] B(2)
D[1] R/Cr[1] B(3)
D[2] R/Cr[2] B(4)
D[3] R/Cr[3] B(5)
D[4] R/Cr[4] B(6)
D[5] R/Cr[5] B(7)
D[6] R/Cr[6] B(8)
D[7] R/Cr[7] B(9)
D[8] G/Y[0] A(2)
D[9] G/Y[1] A(3)
D[10] G/Y[2] A(4)
D[11] G/Y[3] A(5)
D[12] G/Y[4] A(6)
D[13] G/Y[5] A(7)
D[14] G/Y[6] A(8)
D[15] G/Y[7] A(9)
D[16] B/Cb[0] C(2)
D[17] B/Cb[1] C(3)
D[18] B/Cb[2] C(4)
D[19] B/Cb[3] C(5)
D[20] B/Cb[4] C(6)
D[21] B/Cb[5] C(7)
D[22] B/Cb[6] C(8)
D[23] B/Cb[7] C(9)
D[24]
D[25] - -
'0' — C[0]
'0' — C[1]
'0' — A[0]
'0' — A[1]
'0' — B[0]
'0' — B[1]
(1) For 24-bit inputs, the 8 bits for each color shift up two bits, and the two least significant bits of each color are set to '0'.
Table 6-12 V-by-One Data Mapping for 32bpp/24bpp/20bpp YCbCr 4:2:2 (1)
V-by-One DATA MAP MODE 3
V-by-One INPUT DATA BIT 32bpp YCbCr 4:2:2 (2) 24bpp YCbCr 4:2:2 (3) 20bpp YCbCr 4:2:2 MAPPER OUTPUT
D[0] CbCr[8] CbCr[4] CbCr[2] B(2)
D[1] CbCr[9] CbCr[5] CbCr[3] B(3)
D[2] CbCr[10] CbCr[6] CbCr[4] B(4)
D[3] CbCr[11] CbCr[7] CbCr[5] B(5)
D[4] CbCr[12] CbCr[8] CbCr[6] B(6)
D[5] CbCr[13] CbCr[8] CbCr[7] B(7)
D[6] CbCr[14] CbCr[10] CbCr[8] B(8)
D[7] CbCr[15] CbCr[11] CbCr[9] B(9)
D[8] Y[8] Y[4] Y[2] A(2)
D[9] Y[9] Y[5] Y[3] A(3)
D[10] Y[10] Y[6] Y[4] A(4)
D[11] Y[11] Y[7] Y[5] A(5)
D[12] Y[12] Y[8] Y[6] A(6)
D[13] Y[13] Y[9] Y[7] A(7)
D[14] Y[14] Y[10] Y[8] A(8)
D[15] Y[15] Y[11] Y[9] A(9)
'0' — — — C(2)
'0' — — — C(3)
'0' — — — C(4)
'0' — — — C(5)
'0' — — — C(6)
'0' — — — C(7)
'0' — — — C(8)
'0' — — — C(9)
D[24] -
D[25] - - -
'0' — — — C[0]
'0' — — — C[1]
D[28] Y[6] Y[2] Y[2] A[0]
D[29] Y[7] Y[3] Y[3] A[1]
D[30] CbCr[6] CbCr[2] CbCr[2] B[0]
D[31] CbCr[7] CbCr[3] CbCr[3] B[1]
(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".
(2) For 32-bit inputs, the 16 bits per color truncate to 10-bit per color, with the six least significant bits per color discarded.
(3) For 24-bit inputs, the 12 bits per color truncate to 10-bit per color, with the two least significant bits per color discarded.
Table 6-13 V-by-One Data Mapping for 18bpp YCbCr 4:2:2(1)
V-by-One DATA MAP MODE 4
V-by-One INPUT DATA BIT 18bpp YCbCr 4:2:2 (2) MAPPER OUTPUT
D[0] CbCr[1] B(2)
D[1] CbCr[2] B(3)
D[2] CbCr[3] B(4)
D[3] CbCr[4] B(5)
D[4] CbCr[5] B(6)
D[5] CbCr[6] B(7)
D[6] CbCr[7] B(8)
D[7] CbCr[8] B(9)
D[8] Y[1] A(2)
D[9] Y[2] A(3)
D[10] Y[3] A(4)
D[11] Y[4] A(5)
D[12] Y[5] A(6)
D[13] Y[6] A(7)
D[14] Y[7] A(8)
D[15] Y[8] A(9)
'0' — C(2)
'0' — C(3)
'0' — C(4)
'0' — C(5)
'0' — C(6)
'0' — C(7)
'0' — C(8)
'0' — C(9)
D[24]
D[25] - -
'0' — C[0]
'0' — C[1]
'0' — A[0]
D[29] Y[0] A[1]
'0' — B[0]
D[31] CbCr[0] B[1]
(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".
(2) For 18-bit inputs, the 9 bits for each color shift up one bit, and the least significant bits of each color is set to '0'.
Table 6-14 V-by-One Data Mapping for 16bpp YCbCr 4:2:2(1)
V-by-One DATA MAP MODE 5
V-by-One INPUT DATA BIT 16bpp YCbCr 4:2:2 (2) MAPPER OUTPUT
D[0] CbCr[0] B(2)
D[1] CbCr[1] B(3)
D[2] CbCr[2] B(4)
D[3] CbCr[3] B(5)
D[4] CbCr[4] B(6)
D[5] CbCr[5] B(7)
D[6] CbCr[6] B(8)
D[7] CbCr[7] B(9)
D[8] Y[0] A(2)
D[9] Y[1] A(3)
D[10] Y[2] A(4)
D[11] Y[3] A(5)
D[12] Y[4] A(6)
D[13] Y[5] A(7)
D[14] Y[6] A(8)
D[15] Y[7] A(9)
'0' — C(2)
'0' — C(3)
'0' — C(4)
'0' — C(5)
'0' — C(6)
'0' — C(7)
'0' — C(8)
'0' — C(9)
D[24]
D[25] - -
'0' — C[0]
'0' — C[1]
'0' — A[0]
'0' — A[1]
'0' — B[0]
'0' — B[1]
(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".
(2) For 16-bit inputs, the 8 bits for each color shift up one bit, and the least significant bit of each color is set to '0'.
Table 6-15 V-by-One Data Mapping Example for 12bpp/10bpp YCbCr 4:2:0(1)
V-by-One DATA MAP MODE 6
V-by-One INPUT DATA BIT 12bpp YCbCr 4:2:0
EVEN LINE(2) 		12bpp YCbCr 4:2:0
Odd Line (2)		 10bpp YCbCr 4:2:0
EVEN LINE		 10bpp YCbCr 4:2:0
ODD LINE		 MAPPER OUTPUT
D[0] Y01[4] Y01[4] Y01[2] Y11[2] C(2)
D[1] Y01[5] Y01[5] Y01[3] Y11[3] C(3)
D[2] Y01[6] Y01[6] Y01[4] Y11[4] C(4)
D[3] Y01[7] Y01[7] Y01[5] Y11[5] C(5)
D[4] Y01[8] Y01[8] Y01[6] Y11[6] C(6)
D[5] Y01[9] Y01[9] Y01[7] Y11[7] C(7)
D[6] Y01[10] Y01[10] Y01[8] Y11[8] C(8)
D[7] Y01[11] Y01[11] Y01[9] Y11[9] C(9)
D[8] Y00[4] Y00[4] Y00[2] Y10[2] A(2)
D[9] Y00[5] Y00[5] Y00[3] Y10[3] A(3)
D[10] Y00[6] Y00[6] Y00[4] Y10[4] A(4)
D[11] Y00[7] Y00[7] Y00[5] Y10[5] A(5)
D[12] Y00[8] Y00[8] Y00[6] Y10[6] A(6)
D[13] Y00[9] Y00[9] Y00[7] Y10[7] A(7)
D[14] Y00[10] Y00[10] Y00[8] Y10[8] A(8)
D[15] Y00[11] Y00[11] Y00[9] Y10[9] A(9)
D[16] Cb00[4] Cr00[4] Cb00[2] Cr00[2] B(2)
D[17] Cb00[5] Cr00[5] Cb00[3] Cr00[3] B(3)
D[18] Cb00[6] Cr00[6] Cb00[4] Cr00[4] B(4)
D[19] Cb00[7] Cr00[7] Cb00[5] Cr00[5] B(5)
D[20] Cb00[8] Cr00[8] Cb00[6] Cr00[6] B(6)
D[21] Cb00[9] Cr00[9] Cb00[7] Cr00[7] B(7)
D[22] Cb00[10] Cr00[10] Cb00[8] Cr00[8] B(8)
D[23] Cb00[11] Cr00[11] Cb00[9] Cr00[9] B(9)
D[24] - - - - -
D[25] - - - - -
D[26] Cb00[2] Cr00[2] Cb00[0] Cr00[0] B[0]
D[27] Cb00[3] Cr00[3] Cb00[1] Cr00[1] B[1]
D[28] Y00[2] Y10[2] Y00[0] Y10[0] A[0]
D[29] Y00[3] Y10[3] Y00[1] Y10[1] A[1]
D[30] Y01[2] Y11[2] Y01[0] Y11[0] C[0]
D[31] Y01[3] Y11[3] Y01[1] Y11[1] C[1]
(1) For all YCbCr 4:2:0 inputs, two consecutive pixel luma values are brought in on each clock. Even lines carry the Cb values, and odd lines carry the Cr values.
(2) For 12bpp YCbCr 4:2:0 inputs, the 12 bits per color truncate to 10 bits per color with the two least significant bits per color discarded.
Table 6-16 V-by-One Data Mapping Example for 8bpp YCbCr 4:2:0(1)
V-by-One DATA MAP MODE 7
V-by-One INPUT DATA BIT 8bpp YCbCr 4:2:0
EVEN LINE (2)		 8bpp YCbCr 4:2:0
ODD LINE (2)		 MAPPER OUTPUT
D[0] Y01[0] Y11[0] C(2)
D[1] Y01[1] Y11[1] C(3)
D[2] Y01[2] Y11[2] C(4)
D[3] Y01[3] Y11[3] C(5)
D[4] Y01[4] Y11[4] C(6)
D[5] Y01[5] Y11[5] C(7)
D[6] Y01[6] Y11[6] C(8)
D[7] Y01[7] Y11[7] C(9)
D[8] Y00[0] Y10[0] A(2)
D[9] Y00[1] Y10[1] A(3)
D[10] Y00[2] Y10[2] A(4)
D[11] Y00[3] Y10[3] A(5)
D[12] Y00[4] Y10[4] A(6)
D[13] Y00[5] Y10[5] A(7)
D[14] Y00[6] Y10[6] A(8)
D[15] Y00[7] Y10[7] A(9)
D[16] Cb00[0] Cr00[0] B(2)
D[17] Cb00[1] Cr00[1] B(3)
D[18] Cb00[2] Cr00[2] B(4)
D[19] Cb00[3] Cr00[3] B(5)
D[20] Cb00[4] Cr00[4] B(6)
D[21] Cb00[5] Cr00[5] B(7)
D[22] Cb00[6] Cr00[6] B(8)
D[23] Cb00[7] Cr00[7] B(9)
D[24] - - -
D[25] - - -
'0' — — B[0]
'0' — — B[1]
'0' — — A[0]
'0' — — A[1]
'0' — — C[0]
'0' — — C[1]
(1) For all YCbCr 4:2:0 inputs, two consecutive pixel luma values are brought in on each clock. Even lines carry the Cb values, and odd lines carry the Cr values.
(2) For 8bpp YCbCr 4:2:0 inputs, the 8 bits for each color shift up two bits, and the two least significant bits of each color are set to '0'.
Table 6-17 V-by-One Data Mapping Example for 10bpp YCbCr 4:2:0 (1)
V-by-One DATA MAP MODE 8
V-by-One INPUT DATA BIT 10bpp YCbCr 4:2:0
EVEN LINE		 10bpp YCbCr 4:2:0
ODD LINE		 MAPPER OUTPUT
D[0] Y00[2] Y10[2] A(2)
D[1] Y003] Y10[3] A(3)
D[2] Y00[4] Y10[4] A(4)
D[3] Y00[5] Y10[5] A(5)
D[4] Y00[6] Y10[6] A(6)
D[5] Y00[7] Y10[7] A(7)
D[6] Y00[8] Y10[8] A(8)
D[7] Y00[9] Y10[9] A(9)
D[8] Cb00[2] Cr00[2] B(2)
D[9] Cb00[3] Cr00[3] B(3)
D[10] Cb00[4] Cr00[4] B(4)
D[11] Cb00[5] Cr00[5] B(5)
D[12] Cb00[6] Cr00[6] B(6)
D[13] Cb00[7] Cr00[7] B(7)
D[14] Cb00[8] Cr00[8] B(8)
D[15] Cb00[9] Cr00[9] B(9)
D[16] Y01[2] Y11[2] C(2)
D[17] Y01[3] Y11[3] C(3)
D[18] Y01[4] Y11[4] C(4)
D[19] Y01[5] Y11[5] C(5)
D[20] Y01[6] Y11[6] C(6)
D[21] Y01[7] Y11[7] C(7)
D[22] Y01[8] Y11[8] C(8)
D[23] Y01[9] Y11[9] C(9)
D[24] - - -
D[25] - - -
D[26] Y01[0] Y11[0] C[0]
D[27] Y01[1] Y11[1] C[1]
D[28] Cb00[0] Cr00[0] B[0]
D[29] Cb00[1] Cr00[1] B[1]
D[30] Y00[0] Y10[0] A[0]
D[31] Y00[1] Y10[1] A[1]
(1) For all YCbCr 4:2:0 inputs, two consecutive pixel luma values are brought in on each clock. Even lines carry Cb values, and odd lines carry the Cr values.
Table 6-18 V-by-One Data Mapping Example for 8bpp YCbCr 4:2:0 (1)
V-by-One DATA MAP MODE 9
V-by-One INPUT DATA BIT 8bpp YCbCr 4:2:0
EVEN LINE (2)		 8bpp YCbCr 4:2:0
ODD LINE (2)		 MAPPER OUTPUT
D[0] Y00[0] Y10[0] A(2)
D[1] Y00[1] Y10[1] A(3)
D[2] Y00[2] Y10[2] A(4)
D[3] Y003] Y10[3] A(5)
D[4] Y00[4] Y10[4] A(6)
D[5] Y00[5] Y10[5] A(7)
D[6] Y00[6] Y10[6] A(8)
D[7] Y00[7] Y10[7] A(9)
D[8] Cb00[0] Cr00[0] B(2)
D[9] Cb00[1] Cr00[1] B(3)
D[10] Cb00[2] Cr00[2] B(4)
D[11] Cb00[3] Cr00[3] B(5)
D[12] Cb00[4] Cr00[4] B(6)
D[13] Cb00[5] Cr00[5] B(7)
D[14] Cb00[6] Cr00[6] B(8)
D[15] Cb00[7] Cr00[7] B(9)
D[16] Y01[0] Y11[0] C(2)
D[17] Y01[1] Y11[1] C(3)
D[18] Y01[2] Y11[2] C(4)
D[19] Y01[3] Y11[3] C(5)
D[20] Y01[4] Y11[4] C(6)
D[21] Y01[5] Y11[5] C(7)
D[22] Y01[6] Y11[6] C(8)
D[23] Y01[7] Y11[7] C(9)
D[24] - - -
D[25] - - -
'0' — — C[0]
'0' — — C[1]
'0' — — B[0]
'0' — — B[1]
'0' — — A[0]
'0' — — A[1]
(1) For all YCbCr 4:2:0 inputs, two consecutive pixel luma values are brought in on each clock. Even lines carry the Cb values, and odd lines carry the Cr values.
(2) For 8bpp YCbCr 4:2:0 inputs, the 8 bits for each color shift up two bits, and the two least significant bits of each color are set to '0'.