• Menu
  • Product
  • Email
  • PDF
  • Order now

  • DLPC7540 High Resolution Controller

    • DLPS206 May   2021 DLPC7540

      PRODUCTION DATA  

  • CONTENTS
  • SEARCH
  • DLPC7540 High Resolution Controller
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 FPD-Link LVDS Electrical Characteristics
    11. 6.11 USB Electrical Characteristics
    12. 6.12 System Oscillator Timing Requirements
    13. 6.13 Power Supply and Reset Timing Requirements
    14. 6.14 DMD HSSI Timing Requirements
    15. 6.15 DMD Low-Speed LVDS Timing Requirements
    16. 6.16 V-by-One Interface General Timing Requirements
    17. 6.17 FPD-Link Interface General Timing Requirements
    18. 6.18 Source Frame Timing Requirements
    19. 6.19 Synchronous Serial Port Interface Timing Requirements
    20. 6.20 Master and Slave I2C Interface Timing Requirements
    21. 6.21 Programmable Output Clock Timing Requirements
    22. 6.22 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    23. 6.23 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    24. 6.24 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 FPD-Link Interface
      4. 7.3.4 V-by-One interface
      5. 7.3.5 DMD (HSSI) Interface
      6. 7.3.6 Program Memory Flash Interface
      7. 7.3.7 GPIO Supported Functionality
      8. 7.3.8 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
        2. 7.4.2.2 Low Latency Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Management
    2. 9.2 Hot Plug Usage
    3. 9.3 Power Supplies for Unused Input Source Interfaces
    4. 9.4 Power Supplies
      1. 9.4.1 1.15-V Power Supplies
      2. 9.4.2 1.21V Power Supply
      3. 9.4.3 1.8-V Power Supplies
      4. 9.4.4 3.3-V Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Layout Guidelines
      2. 10.1.2  Power Supply Layout Guidelines
      3. 10.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 10.1.4  Layout Guideline for DLPC7540 Reference Clock
        1. 10.1.4.1 Recommended Crystal Oscillator Configuration
      5. 10.1.5  V-by-One Interface Layout Considerations
      6. 10.1.6  FPD-Link Interface Layout Considerations
      7. 10.1.7  USB Interface Layout Considerations
      8. 10.1.8  DMD Interface Layout Considerations
      9. 10.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 10.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 10.2 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Package Data
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
      1. 11.4.1 Video Timing Parameter Definitions
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • ZDC|676
    • MPBGAP5
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • dlps206_oa
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

DLPC7540 High Resolution Controller

1 Features

  • DLPC7540 controller using DLP471TE, DLP471NE, DLP650TE or DLP651NE digital micromirror device (DMD) supports
    • Up to 4K UHD at 60 Hz
    • Up to 1080p at 240 Hz (2D) and 120 Hz (3D)
  • Provides single V-by-One® HS video input port with one, two, four, or eight lanes
    • Up to 600 MHz Pixel clock support
    • Up to 3.0 Gbps input transmission rate
  • Two OpenLDI (FPD-Link I) video input ports with 6-lanes (5 data) per port
  • Input formats supported
    • RGB, YCbCr and ICtCp
    • 4:4:4, 4:2:2, 4:2:0
  • Internal Arm Cortex-R4F processor with FPU
    • 88 configurable GPIOs
    • Programmable PWM generator
    • Programmable capture and delay timers
    • USB 2.0 high-speed OTG controller
    • SPI primary/secondary controllers
    • I2C primary/secondary controllers
    • UART and interrupt controllers
  • Warping engine
    • Improved 1D, 2D and 3D keystone correction
    • Optical distortion correction (radial and lateral color distortion e.g. for short throw )
    • Warping (multi-point manual warp and full warp map access 62x32 points)
    • Blending (manual blending and full bleding map access 63x32 points)
  • Additional image processing
    • DynamicBlack
    • TI DLP BrilliantColor™
    • HDR10 (PQ and HLG) support
    • Frame rate conversion
    • Color coordinate adjustment
    • White color temperature adjustment
    • Programmable degamma
    • Spatial-temporal multiplexing
    • Integrated support for 3-D display
  • Splash screen display and capture
  • Integrated 2G-bit frame memory eliminates need for external high-speed memory
  • External memory support
    • Parallel flash for µP and PWM sequences
    • Secondary flash for Splash Capture, Warping
  • System control
    • DMD power and reset driver control
    • DMD horizontal and vertical image flip
  • JTAG boundary scan test support
  • LED, RGB Laser and Laser Phosphor illuminations

2 Applications

  • Enterprise projector
  • Laser TV
  • Smart projector
  • Digital signage

3 Description

The DLPC7540 is a digital display controller for the 4K UHD and 1080p display chipsets, which comprises of DLPC7540 controller, DLP471TE, DLP471NE, DLP650TE or DLP651NE DMDs and DLPA100 Power and Motor driver. This solution targets display systems that require high resolution and high brightness in a small form factor. To ensure reliable operation, the DLPC7540 controller must always be used with the DLP471TE, DLP471NE, DLP650TE or DLP651NE DMDs and the DLPA100 power management integrated circuit in each application.

Device Information(1)(2)
PART NUMBER PACKAGE BODY SIZE (NOM)
DLPC7540ZDC P-HBGA (676) 31.00 mm × 31.00 mm
(1) For all available packages, see the orderable addendum.
(2) Includes embedded heat slug.
GUID-20201023-CA0I-Z3TS-MPVH-VPSQQ0ZBZXBT-low.gif Figure 3-1 Typical Standalone System

4 Revision History

DATE REVISION NOTES
May 2021 * Initial Release

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale