DLPS253 September   2024 DLPC8445

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     6
    2. 4.1  Initialization, Board Level Test, and Debug
    3. 4.2  V-by-One Interface Input Data and Control
    4. 4.3  FPD Link Port(s) Input Data and Control (Not Supported in DLPC8445)
    5. 4.4  DSI Input Data and Clock (Not Supported in DLPC8445)
    6. 4.5  DMD SubLVDS Interface
    7. 4.6  DMD Reset and Low Speed Interfaces
    8. 4.7  Flash Interface
    9. 4.8  Peripheral Interfaces
    10. 4.9  GPIO Peripheral Interface
    11. 4.10 Clock and PLL Support
    12. 4.11 Power and Ground
    13. 4.12 I/O Type Subscript Definition
    14. 4.13 Internal Pullup and Pulldown Characteristics
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2.     22
    3. 5.2  ESD Ratings
    4. 5.3  Recommended Operating Conditions
    5. 5.4  Thermal Information
    6. 5.5  Power Electrical Characteristics
    7. 5.6  Pin Electrical Characteristics
    8. 5.7  DMD SubLVDS Interface Electrical Characteristics
    9.     29
    10. 5.8  DMD Low Speed Interface Electrical Characteristics
    11.     31
    12. 5.9  V-by-One Interface Electrical Characteristics
    13. 5.10 USB Electrical Characteristics
    14.     34
    15. 5.11 System Oscillator Timing Requirements
    16.     36
    17. 5.12 Power Supply and Reset Timing Requirements
    18.     38
    19. 5.13 V-by-One Interface General Timing Requirements
    20.     40
    21. 5.14 Flash Interface Timing Requirements
    22.     42
    23. 5.15 Source Frame Timing Requirements
    24.     44
    25. 5.16 Synchronous Serial Port Interface Timing Requirements
    26.     46
    27. 5.17 I2C Interface Timing Requirements
    28. 5.18 Programmable Output Clock Timing Requirements
    29. 5.19 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    30.     50
    31. 5.20 DMD Low Speed Interface Timing Requirements
    32.     52
    33. 5.21 DMD SubLVDS Interface Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Sources
      2. 6.3.2 V-by-One Interface
      3. 6.3.3 DMD (SubLVDS) Interface
      4. 6.3.4 Serial Flash Interface
      5. 6.3.5 GPIO Supported Functionality
        1.       63
      6. 6.3.6 Debug Support
  8. 7 Power Supply Recommendations
    1. 7.1 System Power-Up and Power-Down Sequence
    2. 7.2 DMD Fast Park Control (PARKZ)
    3. 7.3 Power Supply Management
    4. 7.4 Hot Plug Usage
    5. 7.5 Power Supplies for Unused Input Source Interfaces
    6. 7.6 Power Supplies
      1. 7.6.1 Power Supplies DLPA3085
  9. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Layout Guideline for DLPC8445 Reference Clock
        1. 8.1.1.1 Recommended Crystal Oscillator Configuration
      2. 8.1.2 V-by-One Interface Layout Considerations
      3. 8.1.3 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      4. 8.1.4 Power Supply Layout Guidelines
    2. 8.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Device Nomenclature
      1. 9.5.1 Device Markings
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
      1. 9.8.1 Video Timing Parameter Definitions
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.4 Serial Flash Interface

The DLPC8445 interfaces to a single external standard/dual/quad SPI serial Flash memory device for configuration and operational data. The 6-pin interface consists of an active low chip select signal, a clock signal, and four bi-directional data signals that can be used to support Standard/Dual/Quad SPI data I/O configurations as necessary during serial flash command execution. Table 6-10 shows a list of supported serial Flash devices that have been validated with the DLPC8445 controller.

Table 6-10 DLPC8445 Supported Standard/Dual/Quad SPI Serial Flash Devices
DENSITY (Mbits) VENDORPART NUMBERPACKAGE SIZE
1.8V Compatible Devices
8MacronixMX25R8035FBHIH2WLCSP
16WinbondW25Q16JWBYIQWLCSP
32MacronixMX25U3232FBHI02WLCSP
64WinbondW25Q64JWBYIQWLCSP
64WinbondW25Q64JWSSIQWLCSP
512GigaDeviceGD25LB512MEYIGWSON
3.3V Compatible Devices
8MacronixMX25R8035FBHIH2WLCSP

The DLPC8445 can potentially support other standard/dual/quad SPI serial flash devices besides those shown in Table 6-10, provided that they have a similar feature set as shown in Table 6-11.

Table 6-11 Feature Requirements for Serial Flash Device Compatibility with DLPC8445
FEATUREREQUIREMENT FOR COMPATIBILITY WITH DLPC8445COMMENTS
SPI data configuration (width)Standard (SingleWire), Dual (Two Wire), Quad (Four Wire)
SPI clocking modeSPI mode 0
SPI clock frequencyup to 60MHz
Clock (↓) to Output Valid time6ns (max)for example, tV or tCLQV
Fast READ addressingAuto-incrementing
Programming modePage mode
Page size256 Bytes
Sector (or Subsector) size4KBRequirederase granularity
Block structureUniform sector / Subsector
Block protection (BP) bitsDisabled (that is, ‘0’) by default
Status register bit(0)Write In Progress (WIP) / BUSY
Status register bit(1)Write enable latch (WEN)
Status register bits(4:2)Block Protection bits (BP[2:0])
Status register bit(7)Status register write protect (SRWP)
Other Status Register bitsNo specific status register bit assignment(s) required. “Other” status register bits often lack common/standard implementation details across vendors/devices. These “other” status register bits/signals can potentially be supported, although generally by the main application only (that is, particularly for devices not listed in Table 6-10).for example, Quad Enable

For compatibility with DLPC8445, serial flash devices must also support the following set of common commands.

Table 6-12 Common Command Set Supported by DLPC8445 Compatible Serial Flash Devices
SPI FLASH
COMMAND		FIRST BYTE
(OP-CODE)		SECOND BYTETHIRD BYTEFOURTH BYTEFIFTH BYTESIXTH BYTENO. OF DUMMY CLOCKSCOMMENTS
Fast READ (1-1-1)0x0BADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)8Variable data payload
Dual READ (1-1-2)0x3BADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)8Variable data payload
2X READ (1-2-2)0xBBADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)4Variable data payload
Quad READ (1-1-4)0x6BADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)8Variable data payload
4X READ (1-4-4)0xEBADDRS(0)ADDRS(1)ADDRS(2)dummyDATA(0)6Variable data payload
Read status0x05STATUS(0)0

STATUS(0) Reg:

bit 1 = WEL

bit 0 = WIP/BUSY
Write status0x01STATUS(0)0
Write Enable0x060
Write Disable0x040
Page program0x02ADDRS(0)ADDRS(1)ADDRS(2)DATA(0)DATA(1)0256 byte data payload
Sector/Subsector
Erase (4KB)		0x20ADDRS(0)ADDRS(1)ADDRS(2)0
Block Erase
(64KB)		0xD8ADDRS(0)ADDRS(1)ADDRS(2)0
Full Chip Erase0xC70
Software Reset
Enable		0x660
Software Reset0x990
Read Id0x9FData(0)Data(1)Data(2)0System only reads 1st three bytes.

SPI data configuration details associated with the various READ commands in the common command set are summarized in Table 6-13.

Table 6-13 Supported READ Command Protocol Implementation Details
READ COMMANDSPI DATA I/O CONFIG FOR OPCODE (# Clocks)SPI DATA I/O CONFIG FOR ADDRESS (# Clocks)NUMBER OF DUMMY CLOCKSSPI DATA I/O CONFIG FOR READ DATA (# Clocks)
Fast Read (1-1-1)Standard (8)Standard (8/byte)8Standard (8/byte)
Dual Read (1-1-2)Standard (8)Standard (8/byte)8Dual (4/byte)
2X Read (1-2-2)Standard (8)Dual (4/byte)4Dual (4/byte)
Quad Read (1-1-4)Standard (8)Standard (8/byte)8Quad (2/byte)
4X Read (1-4-4)Standard (8)Quad (2/byte)6Quad (2/byte)

Host commands issued over the applicable host command interface (that is, I2C or SPI) can be used to program the serial flash device. The host can also specify target flash clock frequency and read command preferences in the flash table for DLPC8445 embedded software to use based on the system’s flash bandwidth requirements.