DLPS253 September 2024 DLPC8445
PRODUCTION DATA
The DLPC8445 contains a test point output port, TSTPT_(7:0), which enables the host to provide controller debug support. For the initial debug operation, the four signals (TSTPT(3:0)) are sampled as inputs approximately 1.5µs after PARKZ goes high (or after a system reset). Once their input state has been sampled and captured, this information is used to set up the initial test mode output state of the TSTPT_(7:0) bus. Table 6-15 defines the test mode selection for a few programmable output states for TSTPT_(7:0). Use the default state of 0000 (defined by the required external pulldown resistors) for normal operation (that is, no debug required).
To allow TI to make use of this debug capability, providing the option of a jumper to an external pullup is recommended for TSTPT(3:0), as well as providing access to allow observation of the TSTPT bus outputs.
TSTPT_(7:0) OUTPUT | TSTPT(3:0) CAPTURED VALUES(1) | ||
---|---|---|---|
0000 (DEFAULT) (NO SWITCHING ACTIVITY) |
0101 CLOCK DEBUG |
1000 SYSTEM CALIBRATION |
|
TSTPT(0) | 0 | HIGH | Vertical Sync |
TSTPT(1) | 0 | 166.25MHz | Delayed CW Index |
TSTPT(2) | 0 | 83.13MHz | Sequence Index |
TSTPT(3) | 0 | 41.56MHz | CW Spoke Test Point |
TSTPT(4) | 0 | 10.39MHz | CW Revolution Test Point |
TSTPT(5) | 0 | 25.16MHz | Reset Sequence Aux Bit 0 |
TSTPT(6) | 0 | 133.00MHz | Reset Sequence Aux Bit 1 |
TSTPT(7) | 0 | HIGH | Reset Sequence Aux Bit 2 |