DLPS253 September   2024 DLPC8445

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     6
    2. 4.1  Initialization, Board Level Test, and Debug
    3. 4.2  V-by-One Interface Input Data and Control
    4. 4.3  FPD Link Port(s) Input Data and Control (Not Supported in DLPC8445)
    5. 4.4  DSI Input Data and Clock (Not Supported in DLPC8445)
    6. 4.5  DMD SubLVDS Interface
    7. 4.6  DMD Reset and Low Speed Interfaces
    8. 4.7  Flash Interface
    9. 4.8  Peripheral Interfaces
    10. 4.9  GPIO Peripheral Interface
    11. 4.10 Clock and PLL Support
    12. 4.11 Power and Ground
    13. 4.12 I/O Type Subscript Definition
    14. 4.13 Internal Pullup and Pulldown Characteristics
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2.     22
    3. 5.2  ESD Ratings
    4. 5.3  Recommended Operating Conditions
    5. 5.4  Thermal Information
    6. 5.5  Power Electrical Characteristics
    7. 5.6  Pin Electrical Characteristics
    8. 5.7  DMD SubLVDS Interface Electrical Characteristics
    9.     29
    10. 5.8  DMD Low Speed Interface Electrical Characteristics
    11.     31
    12. 5.9  V-by-One Interface Electrical Characteristics
    13. 5.10 USB Electrical Characteristics
    14.     34
    15. 5.11 System Oscillator Timing Requirements
    16.     36
    17. 5.12 Power Supply and Reset Timing Requirements
    18.     38
    19. 5.13 V-by-One Interface General Timing Requirements
    20.     40
    21. 5.14 Flash Interface Timing Requirements
    22.     42
    23. 5.15 Source Frame Timing Requirements
    24.     44
    25. 5.16 Synchronous Serial Port Interface Timing Requirements
    26.     46
    27. 5.17 I2C Interface Timing Requirements
    28. 5.18 Programmable Output Clock Timing Requirements
    29. 5.19 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    30.     50
    31. 5.20 DMD Low Speed Interface Timing Requirements
    32.     52
    33. 5.21 DMD SubLVDS Interface Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Sources
      2. 6.3.2 V-by-One Interface
      3. 6.3.3 DMD (SubLVDS) Interface
      4. 6.3.4 Serial Flash Interface
      5. 6.3.5 GPIO Supported Functionality
        1.       63
      6. 6.3.6 Debug Support
  8. 7 Power Supply Recommendations
    1. 7.1 System Power-Up and Power-Down Sequence
    2. 7.2 DMD Fast Park Control (PARKZ)
    3. 7.3 Power Supply Management
    4. 7.4 Hot Plug Usage
    5. 7.5 Power Supplies for Unused Input Source Interfaces
    6. 7.6 Power Supplies
      1. 7.6.1 Power Supplies DLPA3085
  9. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Layout Guideline for DLPC8445 Reference Clock
        1. 8.1.1.1 Recommended Crystal Oscillator Configuration
      2. 8.1.2 V-by-One Interface Layout Considerations
      3. 8.1.3 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      4. 8.1.4 Power Supply Layout Guidelines
    2. 8.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Device Nomenclature
      1. 9.5.1 Device Markings
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
      1. 9.8.1 Video Timing Parameter Definitions
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.1 Initialization, Board Level Test, and Debug

PINI/O (1)DESCRIPTION
NAMENO.
PROJ_ONAP2I1Normal mirror parking request (active low): To be driven by the PROJ_ON output of the host. A logic low on this signal causes the Controller to PARK the DMD, but it does not power down the DMD (the DLPA does that instead). The minimum high time is 200ms. The minimum low time is 200ms.
RESETZP2I1Power-on reset (active low input with a hysteresis buffer). Self-configuration starts when a low-to-high transition is detected on RESETZ. All controller power and clocks must be stable before this reset is de-asserted. No signals are in their active state while RESETZ is asserted. This pin is typically connected to the RESETZ pin of the DLPA PMIC.
PARKZAR1I1DMD fast park control (active low Input with a hysteresis buffer). This signal is used to quickly park the DMD when loss of power is imminent. The longest lifetime of the DMD may not be achieved with the fast park operation; therefore, this signal is intended to only be asserted when a normal park operation is unable to be completed. The PARKZ signal is typically provided from the DLPA interrupt output signal.
JTAGTCKV24I2JTAG and ARM-ICE Serial Data Clock. This signal is shared between JTAG and ARM-ICE (TI test only), operation. Includes a weak internal pulldown
JTAGTMS1U23I2JTAG Test Mode Select. Includes a weak internal pullup
JTAGTMS2W25I2ARM-ICE Test Mode Select
For normal operation, this pin must be left open or unconnected. Includes a weak internal pullup
JTAGTRSTZAA25I2JTAG, ARM-ICE Reset.
For normal operation, this pin must be pulled to ground through an external resistor with value 8kΩ or less. Failure to pull this pin low during normal operation causes start-up and initialization problems.
For JTAG Boundary Scan and ARM-ICE Debug operation, this pin must be pulled up or left disconnected. Includes a weak internal pullup and hysteresis
JTAGTDIY24I2JTAG, ARM-ICE, and CPU MBIST: Serial Data In. Includes weak internal pullups
JTAGTDO1V22B14JTAG Serial Data Out
JTAGTDO2W23B14ARM-ICE Serial Data Out. For normal operation, this pin requires an external pullup resistor with a value of ≤ 9.15kΩ.
ETM_TRACECLKU25O14Reserved Pin, must be left unconnected.
ETM_TRACECTLT24O14Reserved Pin, must be left unconnected.
TSTPT_0T22B14Test pin 0
This pin has an internal pulldown and may require an external pullup resistor (no pullup: Normal Boot, pullup: Wait for Host commands) with a value of ≤ 9.15kΩ.
TSTPT_1R25B14Test pin 1
This pin has an internal pulldown for Normal Boot operation.
TSTPT_2R23B14Test pin 2
This pin has an internal pulldown and may require an external pullup resistor (no pullup: I2C address = 0x36, pullup: I2C address = 0x34) with a value of ≤ 9.15kΩ.
TSTPT_3P24B14Test pin 3
This pin has an internal pulldown and may require an external pullup resistor (no pullup: Host interface is USB or I2C, pullup: Host interface is I2C only) with a value of ≤ 9.15kΩ.
TSTPT_4N25B14Test pin 4
This pin has an internal pulldown resistor.
TSTPT_5P22B14Test pin 5
This pin has an internal pulldown resistor.
TSTPT_6N23B14Test pin 6
This pin has an internal pulldown resistor.
TSTPT_7M24B14Test pin 7
This pin has an internal pulldown resistor.
GPTP0AA23B13General Purpose Test pin 0
This pin has an internal pulldown and may require an external pullup resistor (no pullup: external crystal, pullup: external clock) with a value of ≤ 9.15kΩ.
GPTP1AB22B13General Purpose Test pin 1
This pin has an internal pulldown resistor.
GPTP2AC25B13General Purpose Test pin 2
This pin has an internal pulldown resistor.
ATB_0_HAH4PWRReserved Pin, must be left unconnected.
ATB_1_HAJ5PWRReserved Pin, must be left unconnected.
ATESTG13PWRReserved Pin, must be left unconnected.
CAP_VDDS_FLSHAD22PWRExternal bias capacitance
CAP_VDDS_INTFAJ21PWRExternal bias capacitance
IFORCEL3PWRManufacturing use only. Must be tied to ground.
VSENSEK2PWRReserved Pin, must be left unconnected.
HWTEST_ENY22I2Reserved Pin.
This signal must be connected directly to ground on the PCB for normal operation. Includes a weak internal pulldown and hysteresis
(1) See Section 4.12 for more information on I/O definitions.