DLPS037H October 2014 – June 2024 DLPC900
PRODUCTION DATA
The DLPC900 controller provides the pattern data to the DMD over a double data rate (DDR) interface. Table 7-7 describes the signals used for this interface.
SIGNAL NAME | DESCRIPTION | |||
---|---|---|---|---|
DDA(15:0) | DMD, LVDS interface channel A, differential serial data | |||
DDB(15:0) | DMD, LVDS interface channel B, differential serial data | |||
DCKA | DMD, LVDS interface channel A, differential clock | |||
DCKB | DMD, LVDS interface channel B, differential clock | |||
SCA | DMD, LVDS interface channel A, differential serial control | |||
SCB | DMD, LVDS interface channel B, differential serial control |
The DLPC900 controls the micromirror clock pulses in a manner to ensure proper and reliable operation of the DMD.
SIGNAL NAME | DESCRIPTION | |||
---|---|---|---|---|
DADOEZ | DMD output-enable (active low) | |||
DADADDR(3:0) | DMD address | |||
DADMODE(1:0) | DMD mode | |||
DADSEL(1:0) | DMD select | |||
DADSTRB | DMD strobe | |||
DAD_INTZ | DMD interrupt (active low). This signal requires an external 1KΩ pullup and uses hysteresis. |
The DLPC900 controls the micromirror control interface signals in a manner to ensure proper and reliable operation of the DMD.