DLPS037H October   2014  – June 2024 DLPC900

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  System Oscillators Timing Requirements #GUID-909D0FD3-84C7-4481-924A-4FDE7EB548A1/DLPS0373944
    7. 5.7  Power-Up and Power-Down Timing Requirements
      1. 5.7.1 Power-Up
      2. 5.7.2 Power-Down
    8. 5.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 5.9  JTAG Interface: I/O Boundary Scan Application Switching Characteristics
    10. 5.10 Programmable Output Clocks Switching Characteristics
    11. 5.11 Port 1 and 2 Input Pixel Interface Timing Requirements
    12. 5.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
    13. 5.13 Synchronous Serial Port (SSP) Switching Characteristics
    14. 5.14 DMD Interface Switching Characteristics
    15. 5.15 DMD LVDS Interface Switching Characteristics
    16. 5.16 Source Input Blanking Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DMD Configurations
      2. 6.3.2 Video Timing Input Blanking Specification
      3. 6.3.3 Board-Level Test Support
      4. 6.3.4 Two Controller Considerations
      5. 6.3.5 Memory Design Considerations
        1. 6.3.5.1 Flash Memory Optimization
        2. 6.3.5.2 Operating Modes
        3. 6.3.5.3 DLPC900 External Memory Space
        4. 6.3.5.4 Minimizing Memory Space
        5. 6.3.5.5 Minimizing Board Size
          1. 6.3.5.5.1 Package Selection
          2. 6.3.5.5.2 Large Density Flash
            1. 6.3.5.5.2.1 Combining Two Chip-Selects with One 32-Megabyte Flash
            2. 6.3.5.5.2.2 Combining Three Chip-Selects with One 64-Megabyte Flash
            3. 6.3.5.5.2.3 Combining Three Chip-Selects with One 128-Megabyte Flash
        6. 6.3.5.6 Minimizing Board Space
        7. 6.3.5.7 Flash Memory
    4. 6.4 Device Functional Modes
      1. 6.4.1 Structured Light Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Two Controller Chipset
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 DLPC900 System Interfaces
            1. 7.2.1.2.1.1 Control Interface
            2. 7.2.1.2.1.2 Input Data Interfaces
            3. 7.2.1.2.1.3 DLPC900 System Output Interfaces
              1. 7.2.1.2.1.3.1 Illumination Interface
              2. 7.2.1.2.1.3.2 Trigger and Sync Interface
            4. 7.2.1.2.1.4 DLPC900 System Support Interfaces
              1. 7.2.1.2.1.4.1 Reference Clock and PLL
              2. 7.2.1.2.1.4.2 Program Memory Flash Interface
              3. 7.2.1.2.1.4.3 DMD Interface
      2. 7.2.2 Typical Single Controller Chipset
  9. 8 Power Supply Recommendations
    1. 8.1 System Power Regulation
      1. 8.1.1 Power Distribution System
        1. 8.1.1.1 1.15V System Power
        2. 8.1.1.2 1.8V System Power
        3. 8.1.1.3 3.3-V System Power
    2. 8.2 System Environment and Defaults
      1. 8.2.1 DLPC900 System Power-Up and Reset Default Conditions
    3. 8.3 System Power-Up Sequence
      1. 8.3.1 Power-On Sense (POSENSE) Support
      2. 8.3.2 Power Good (PWRGOOD) Support
      3. 8.3.3 5V Tolerant Support
    4. 8.4 System Reset Operation
      1. 8.4.1 Power-Up Reset Operation
      2. 8.4.2 System Reset Operation
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General PCB Recommendations
      2. 9.1.2  PCB Layout Guidelines for Internal Controller PLL Power
      3. 9.1.3  PCB Layout Guidelines for Quality Video Performance
      4. 9.1.4  Recommended MOSC Crystal Oscillator Configuration
      5. 9.1.5  Spread Spectrum Clock Generator Support
      6. 9.1.6  GPIO Interface
      7. 9.1.7  General Handling Guidelines for Unused CMOS-Type Pins
      8. 9.1.8  DMD Interface Considerations
        1. 9.1.8.1 Flex Connector Plating
      9. 9.1.9  PCB Design Standards
      10. 9.1.10 Signal Layers
      11. 9.1.11 Trace Widths and Minimum Spacing
      12. 9.1.12 Trace Impedance and Routing Priority
      13. 9.1.13 Power and Ground Planes
      14. 9.1.14 Power Vias
      15. 9.1.15 Decoupling
      16. 9.1.16 Fiducials
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Device Markings
      3. 10.1.3 DEFINITIONS—Video Timing Parameters
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.11 Port 1 and 2 Input Pixel Interface Timing Requirements

MINMAXUNIT
ƒclockClock frequency, P_CLK1, P_CLK2, P_CLK3 (24-bit busSection 6.3.5.6)12175MHz
ƒclockClock frequency, P_CLK1, P_CLK2, P_CLK3 (48-bit busSection 6.3.5.6)
See Section 5.12.		12141MHz
tcCycle time, P_CLK1, P_CLK2, P_CLK35.71483.33ns
tw(H)Pulse duration, high50% to 50% reference points (signal)2.3ns
tw(L)Pulse duration, low50% to 50% reference points (signal)2.3ns
tjpClock period jitter P_CLK1, P_CLK2, P_CLK3
(that is, the deviation in period from ideal period)		Max fclockSee (1)ps
ttTransition time, tt = tf / tr, P_CLK1, P_CLK2, P_CLK320% to 80% reference points (signal)0.62.0ns
ttTransition time, tt = tf / tr, P1_A(9:0), P1_B(9:0) , P1_C(9:0), P1_HSYNC, P1_VSYNC, P1_DATEN20% to 80% reference points (signal)0.63.0ns
ttTransition time, tt = tf / tr20% to 80% reference points (signal)0.63.0ns
tsuSetup time, P1_A(9:0), valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P1_A(9:0), valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tsuSetup time, P1_B(9:0), valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P1_B(9:0), valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tsuSetup time, P1_C(9:0), valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P1_C(9:0), valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tsuSetup time, P1_VSYNC, valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P1_VSYNC, valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tsuSetup time, P1_HSYNC, valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P1_HSYNC, valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tsuSetup time, P2_A(9:0), valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P2_A(9:0), valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tsuSetup time, P2_B(9:0), valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P2_B(9:0), valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tsuSetup time, P2_C(9:0), valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P2_C(9:0), valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tsuSetup time, P2_VSYNC, valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P2_VSYNC, valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tsuSetup time, P2_HSYNC, valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P2_HSYNC, valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tsuSetup time, P_DATEN1, valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P_DATEN1, valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tsuSetup time, P_DATEN2, valid before P_CLK1, P_CLK2, or P_CLK30.8ns
thHold time, P_DATEN2, valid after P_CLK1, P_CLK2, or P_CLK30.8ns
tw(A)VSYNC active pulse duration1Video line
tw(A)HSYNC active pulse duration16Pixel clocks
(1) For frequencies (ƒclock) less than 175MHz, use the following formula to obtain the jitter: Max clock jitter = ± [(1 / ƒclock) – 5414ps].
DLPC900 Input Port 1 and 2 InterfaceFigure 5-8 Input Port 1 and 2 Interface