DLPS037H October   2014  – June 2024 DLPC900

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  System Oscillators Timing Requirements #GUID-909D0FD3-84C7-4481-924A-4FDE7EB548A1/DLPS0373944
    7. 5.7  Power-Up and Power-Down Timing Requirements
      1. 5.7.1 Power-Up
      2. 5.7.2 Power-Down
    8. 5.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 5.9  JTAG Interface: I/O Boundary Scan Application Switching Characteristics
    10. 5.10 Programmable Output Clocks Switching Characteristics
    11. 5.11 Port 1 and 2 Input Pixel Interface Timing Requirements
    12. 5.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
    13. 5.13 Synchronous Serial Port (SSP) Switching Characteristics
    14. 5.14 DMD Interface Switching Characteristics
    15. 5.15 DMD LVDS Interface Switching Characteristics
    16. 5.16 Source Input Blanking Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DMD Configurations
      2. 6.3.2 Video Timing Input Blanking Specification
      3. 6.3.3 Board-Level Test Support
      4. 6.3.4 Two Controller Considerations
      5. 6.3.5 Memory Design Considerations
        1. 6.3.5.1 Flash Memory Optimization
        2. 6.3.5.2 Operating Modes
        3. 6.3.5.3 DLPC900 External Memory Space
        4. 6.3.5.4 Minimizing Memory Space
        5. 6.3.5.5 Minimizing Board Size
          1. 6.3.5.5.1 Package Selection
          2. 6.3.5.5.2 Large Density Flash
            1. 6.3.5.5.2.1 Combining Two Chip-Selects with One 32-Megabyte Flash
            2. 6.3.5.5.2.2 Combining Three Chip-Selects with One 64-Megabyte Flash
            3. 6.3.5.5.2.3 Combining Three Chip-Selects with One 128-Megabyte Flash
        6. 6.3.5.6 Minimizing Board Space
        7. 6.3.5.7 Flash Memory
    4. 6.4 Device Functional Modes
      1. 6.4.1 Structured Light Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Two Controller Chipset
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 DLPC900 System Interfaces
            1. 7.2.1.2.1.1 Control Interface
            2. 7.2.1.2.1.2 Input Data Interfaces
            3. 7.2.1.2.1.3 DLPC900 System Output Interfaces
              1. 7.2.1.2.1.3.1 Illumination Interface
              2. 7.2.1.2.1.3.2 Trigger and Sync Interface
            4. 7.2.1.2.1.4 DLPC900 System Support Interfaces
              1. 7.2.1.2.1.4.1 Reference Clock and PLL
              2. 7.2.1.2.1.4.2 Program Memory Flash Interface
              3. 7.2.1.2.1.4.3 DMD Interface
      2. 7.2.2 Typical Single Controller Chipset
  9. 8 Power Supply Recommendations
    1. 8.1 System Power Regulation
      1. 8.1.1 Power Distribution System
        1. 8.1.1.1 1.15V System Power
        2. 8.1.1.2 1.8V System Power
        3. 8.1.1.3 3.3-V System Power
    2. 8.2 System Environment and Defaults
      1. 8.2.1 DLPC900 System Power-Up and Reset Default Conditions
    3. 8.3 System Power-Up Sequence
      1. 8.3.1 Power-On Sense (POSENSE) Support
      2. 8.3.2 Power Good (PWRGOOD) Support
      3. 8.3.3 5V Tolerant Support
    4. 8.4 System Reset Operation
      1. 8.4.1 Power-Up Reset Operation
      2. 8.4.2 System Reset Operation
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General PCB Recommendations
      2. 9.1.2  PCB Layout Guidelines for Internal Controller PLL Power
      3. 9.1.3  PCB Layout Guidelines for Quality Video Performance
      4. 9.1.4  Recommended MOSC Crystal Oscillator Configuration
      5. 9.1.5  Spread Spectrum Clock Generator Support
      6. 9.1.6  GPIO Interface
      7. 9.1.7  General Handling Guidelines for Unused CMOS-Type Pins
      8. 9.1.8  DMD Interface Considerations
        1. 9.1.8.1 Flex Connector Plating
      9. 9.1.9  PCB Design Standards
      10. 9.1.10 Signal Layers
      11. 9.1.11 Trace Widths and Minimum Spacing
      12. 9.1.12 Trace Impedance and Routing Priority
      13. 9.1.13 Power and Ground Planes
      14. 9.1.14 Power Vias
      15. 9.1.15 Decoupling
      16. 9.1.16 Fiducials
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Device Markings
      3. 10.1.3 DEFINITIONS—Video Timing Parameters
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.8 DMD Interface Considerations

High-speed interface waveform quality and timing on the DLPC900 controller (that is, the LVDS DMD interface) is dependent on the following factors:

  • Total length of the interconnect system
  • Spacing between traces
  • Characteristic impedance
  • Etch losses
  • How well matched the lengths are across the interface

Thus, ensuring positive timing margin requires attention to many factors.

As an example, DMD interface system timing margin can be calculated as follows:

Equation 4. Setup Margin = (controller output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)
Equation 5. Hold-time Margin = (controller output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)

The PCB SI degradation is the signal integrity degradation due to PCB affects which includes such things as simultaneously switching output (SSO) noise, crosstalk, and intersymbol interference (ISI) noise.

DLPC900 I/O timing parameters, as well as DMD I/O timing parameters, can be easily found in their corresponding data sheets. Similarly, PCB routing mismatch can be easily budgeted and met via controlled PCB routing. However, PCB SI degradation is not as easy-to-determine.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines provide a reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Deviation from these recommendations can work, but must be confirmed with PCB signal integrity analysis or lab measurements.

PCB design: Refer to the Figure 9-5.
Configuration:
Etch thickness (T):
Flex etch thickness (T):
Single-ended signal impedance:
Differential signal impedance:		Asymmetric dual stripline
1.0oz copper (1.2mil)
0.5oz copper (0.6mil)
50Ω (±10%)
100Ω (±10%)
PCB stackup: Refer to the Figure 9-5.
Reference plane 1 is assumed to be a ground plane for proper return path.
Reference plane 2 is assumed to be the I/O power plane or ground.
Dielectric FR4, (Er):4.2 (nominal)
Signal trace distance to reference plane 1 (H1):5.0mil (nominal)
Signal trace distance to reference plane 2 (H2):34.2mil (nominal)
DLPC900 PCB Stackup GeometriesFigure 9-5 PCB Stackup Geometries
Table 9-3 General PCB Routing (Applies to All Corresponding PCB Signals (Refer to Figure 9-5.)
PARAMETERAPPLICATIONSINGLE-ENDED SIGNALSDIFFERENTIAL PAIRSUNIT
Line width (W)Escape routing in ball field4
(0.1)		4
(0.1)		mil
(mm)
PCB etch data or control7
(0.18)		4.25
(0.11)		mil
(mm)
PCB etch clocks7
(0.18)		4.25
(0.11)		mil
(mm)
Differential signal pair spacing (S)PCB etch data or controlN/A5.75 (1)
(0.15)		mil
(mm)
PCB etch clocksN/A5.75 (1)
(0.15)		mil
(mm)
Minimum differential pair-to-pair spacing (S)PCB etch data or controlN/A20
(0.51)		mil
(mm)
PCB etch clocksN/A20
(0.51)		mil
(mm)
Minimum line spacing to other signals (S)Escape routing in ball field4
(0.1)		4
(0.1)		mil
(mm)
PCB etch data or control10
(0.25)		20
(0.51)		mil
(mm)
PCB etch clocks20
(0.51)		20
(0.51)		mil
(mm)
Maximum differential pair P-to-N length mismatchTotal dataN/A12
(0.3)		mil
(mm)
Total clockN/A12
(0.3)		mil
(mm)
(1) Spacing can vary to maintain differential impedance requirements.
Table 9-4 DMD Interface Specific PCB Routing
SIGNAL GROUP LENGTH MATCHING
INTERFACESIGNAL GROUPREFERENCE SIGNALMAX MISMATCHUNIT
DMD
(LVDS)		SCA_P/ SCA_N
DDA_P_(15:0)/ DDA_N_(15:0)		DCKA_P/ DCKA_N± 150
(± 3.81)		mil
(mm)
DMD
(LVDS)		SCB_P/ SCB_N
DDB_P_(15:0)/ DDB_N_(15:0)		DCKB_P/ DCKB_N± 150
(± 3.81)		mil
(mm)

When routing the DMD Interface signals it is recommended to:

  • Minimize the number of layer changes for single-ended signals.
  • Individual differential pairs can be routed on different layers but the signals of a given pair must not change layers.
Table 9-5 DMD Signal Routing Length(1)
BUSMINMAXUNIT
DMD
(LVDS)		50375mm
(1) Max signal routing length includes escape routing.

Stubs: Avoid stubs.

Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100Ω internally.

Connector (DMD-LVDS interface bus only):

High-speed connectors that meet the following requirements can be used:

  • Differential crosstalk: < 5%
  • Differential impedance: 75Ω to 125Ω

Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs must be routed in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference for each row must be accounted for on associated PCB etch lengths.

These guidelines will produce a maximum PCB routing mismatch of 4.41mm (0.174 inch) or approximately 30.4ps, assuming 175ps/inch FR4 propagation delay.

These PCB routing guidelines will result in approximately 25ps system setup margin and 25ps system hold margin for the DMD interface after accounting for signal integrity degradation as well as routing mismatch.

Both the DLPC900 output timing parameters and the DMD input timing parameters include timing budget to account for their respective internal package routing skew.