DLPS037H October 2014 – June 2024 DLPC900
PRODUCTION DATA
The DLPC900 provides three external program memory chip selects for standard NOR-type flash plus two optional GPIOs for extended external memory access (GPIO_45, GPIO_46):
Flash access timing is programmable up to 19 wait-states. Table 7-6 contains the formulas to calculate the required wait-states for each of the parameters shown in Figure 7-3 for a typical flash device. Refer to the DLPC900 Programmers Guide for details on how to set new wait-state values.
PARAMETER | FORMULA (1) | DEFAULT | |
---|---|---|---|
TCS (CSZ low to WEZ low ) | = Roundup((TCS+ 5ns) / 6.7ns) | 2 | |
TWP (WEZ low to WEZ high) | = Roundup((TWP+ 5ns) / 6.7ns) | 11 | |
TCH (WEZ high to CSZ high ) | = Roundup((TCH+ 5ns) / 6.7ns) | 2 | |
TACC (CSZ low to Output Valid ) (2) | = Roundup((TACC+ 5ns) / 6.7ns) | 19 | |
Maximum supported wait-states | 19 (120ns) (3) |