DLPS167A March 2024 – September 2024 DLPC964
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The controller reset input SYS_ARSTZ is an active low, asynchronous reset. Asserting SYS_ARSTZ low will reset the logic in the DLPC964 controller back to the default state just after the configuration is complete. This reset can be sourced from the Applications FPGA or from the customer front end.