DLPS167A March 2024 – September 2024 DLPC964
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
fcgt | Clock frequency, GTTX_CHn_REFCLK(1) and GTRX_CHn_REFCLK(1) | 100 | MHz | |||
fcui | Clock frequency, REFCLK_UI(1) | 156.25 | MHz | |||
fcs | Clock frequency, SYS_CLK100(1) | 100 | MHz | |||
fcdmd | Clock frequency, DMD_GTREFCLK_IN_n(1) | 112.5 | MHz | |||
tcgt | Cycle time, GTRX_CHn_REFCLK | 10 | ns | |||
tw(H) | Pulse duration, high | 50% to 50% reference points (signal) | 5 | ns | ||
tw(L) | Pulse duration, low | 50% to 50% reference points (signal) | 5 | ns | ||
tt | Transition time, tt = tf / tr | 20% to 80% reference points (signal) | 200 | ps | ||
tjp | Period Jitter CHn_GTRX | Total Sinusoidal Period Jitter | 0.3 | UI | ||
tsk | Skew, CHn_GTRX(1) | Lane to lane within a single Input Channel | 200 | ps |