DLPS167A March 2024 – September 2024 DLPC964
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The high-speed interface between the applications FPGA and DLPC964 controller allows the use of the user K-data interface within the Aurora 64B/66B Streaming Protocol. The following signals are used in this interface:
Use these bits to transmit information across the high-speed interface between the DLPC964 controller and the applications FPGA. USERK 0x0 packet bits 76:72 are available as follows: