DLPS167A March 2024 – September 2024 DLPC964
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The FPGA_INTERRUPT_STATUS register contains the status for the Watchdog timeout and the four Aurora 64B/66B Channels Hard Error status. A '1' can be written to these registers to clear their status.
Bit(s) | Description | Reset | Type | Notes |
---|---|---|---|---|
0 | Fieldname: Reserved | 0x0 | ||
1 | SPARE | 0x0 | ||
2 | Fieldname: ERROR_RSC_WATCHDOG_FLD | 0x0 | I | |
Watchdog timeout. No DMD block reset occurred for 10 seconds. | ||||
Write '1' to clear this error status bit. | ||||
3 | Fieldname: HSS_CH0_HARD_ERROR_FLD | 0x0 | I | |
Input Aurora Channel 0 hard error | ||||
(This indicates the HSS requires a reset 0x0200 to recover from a hard error condition.) | ||||
Write '1' to clear this error status bit. | ||||
4 | Fieldname: HSS_CH1_HARD_ERROR_FLD | 0x0 | I | |
Input Aurora Channel 1 hard error | ||||
(This indicates the HSS requires a reset 0x0200 to recover from a hard error condition.) | ||||
Write '1' to clear this error status bit. | ||||
5 | Fieldname: HSS_CH2_HARD_ERROR_FLD | 0x0 | I | |
Input Aurora Channel 2 hard error | ||||
(This indicates the HSS requires a reset 0x0200 to recover from a hard error condition.) | ||||
Write '1' to clear this error status bit. | ||||
6 | Fieldname: HSS_CH3_HARD_ERROR_FLD | 0x0 | I | |
Input Aurora Channel 3 hard error | ||||
(This indicates the HSS requires a reset 0x0200 to recover from a hard error condition.) | ||||
Write '1' to clear this error status bit. | ||||
7 | SPARE | 0x0 | ||
31:8 | UNUSED | 0x0 |