SPRS976E November   2016  – May 2018 DM505

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  SD_DAC
      4. 4.3.4  ADC
      5. 4.3.5  Camera Control
      6. 4.3.6  CPI
      7. 4.3.7  CSI2
      8. 4.3.8  EMIF
      9. 4.3.9  GPMC
      10. 4.3.10 Timers
      11. 4.3.11 I2C
      12. 4.3.12 UART
      13. 4.3.13 McSPI
      14. 4.3.14 QSPI
      15. 4.3.15 McASP
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 SDIO Controller
      19. 4.3.19 GPIO
      20. 4.3.20 ePWM
      21. 4.3.21 Emulation and Debug Subsystem
      22. 4.3.22 System and Miscellaneous
        1. 4.3.22.1 Sysboot
        2. 4.3.22.2 Power, Reset and Clock Management (PRCM)
        3. 4.3.22.3 Enhanced Direct Memory Access (EDMA)
        4. 4.3.22.4 Interrupt Controllers (INTC)
      23. 4.3.23 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-6   LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7   Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8   IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9   IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS Analog OSC Buffers DC Electrical Characteristics
      6. Table 5-11 LVCMOS CSI2 DC Electrical Characteristics
      7. Table 5-12 Dual Voltage LVCMOS DC Electrical Characteristics
      8. Table 5-13 Analog-to-Digital ADC Subsystem Electrical Specifications
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Timing Requirements and Switching Characteristics
      1. 5.9.1 Timing Parameters and Information
        1. 5.9.1.1 Parameter Information
          1. 5.9.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.9.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.9.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.9.2 Interface Clock Specifications
        1. 5.9.2.1 Interface Clock Terminology
        2. 5.9.2.2 Interface Clock Frequency
      3. 5.9.3 Power Supply Sequences
      4. 5.9.4 Clock Specifications
        1. 5.9.4.1 Input Clocks / Oscillators
          1. 5.9.4.1.1 OSC0 External Crystal
          2. 5.9.4.1.2 OSC0 Input Clock
          3. 5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.9.4.1.3.1 OSC1 External Crystal
            2. 5.9.4.1.3.2 OSC1 Input Clock
          4. 5.9.4.1.4 RC On-die Oscillator Clock
        2. 5.9.4.2 Output Clocks
        3. 5.9.4.3 DPLLs, DLLs
          1. 5.9.4.3.1 DPLL Characteristics
          2. 5.9.4.3.2 DLL Characteristics
            1. 5.9.4.3.2.1 DPLL and DLL Noise Isolation
      5. 5.9.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.9.6 Peripherals
        1. 5.9.6.1  Timing Test Conditions
        2. 5.9.6.2  VIP
        3. 5.9.6.3  DSS
        4. 5.9.6.4  ISS
          1. 5.9.6.4.1 CSI-2 MIPI D-PHY—1.5 V and 1.8 V
        5. 5.9.6.5  EMIF
        6. 5.9.6.6  GPMC
          1. 5.9.6.6.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.9.6.6.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.9.6.6.3 GPMC/NAND Flash Interface Asynchronous Timing
        7. 5.9.6.7  GP Timers
          1. 5.9.6.7.1 GP Timer Features
        8. 5.9.6.8  I2C
          1. Table 5-41 Timing Requirements for I2C Input Timings
          2. Table 5-42 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        9. 5.9.6.9  UART
          1. Table 5-43 Timing Requirements for UART
          2. Table 5-44 Switching Characteristics Over Recommended Operating Conditions for UART
        10. 5.9.6.10 McSPI
        11. 5.9.6.11 QSPI
        12. 5.9.6.12 McASP
          1. Table 5-52 Timing Requirements for McASP1
          2. Table 5-53 Timing Requirements for McASP2
          3. Table 5-54 Timing Requirements for McASP3
          4. Table 5-55 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-56 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-57 Switching Characteristics Over Recommended Operating Conditions for McASP3
        13. 5.9.6.13 DCAN and MCAN
          1. 5.9.6.13.1  DCAN
          2. 5.9.6.13.2  MCAN
          3. Table 5-60 Timing Requirements for CAN Receive
          4. Table 5-61 Switching Characteristics Over Recommended Operating Conditions for CAN Transmit
        14. 5.9.6.14 GMAC_SW
          1. 5.9.6.14.1 GMAC MDIO Interface Timings
          2. 5.9.6.14.2 GMAC RGMII Timings
            1. Table 5-65 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-66 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-67 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-68 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        15. 5.9.6.15 SDIO Controller
          1. 5.9.6.15.1 MMC, SD Default Speed
          2. 5.9.6.15.2 MMC, SD High Speed
          3. 5.9.6.15.3 MMC, SD and SDIO SDR12 Mode
          4. 5.9.6.15.4 MMC, SD SDR25 Mode
        16. 5.9.6.16 GPIO
      7. 5.9.7 Emulation and Debug Subsystem
        1. 5.9.7.1 JTAG Electrical Data/Timing
          1. Table 5-79 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 5-80 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 5-81 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 5-82 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.9.7.2 Trace Port Interface Unit (TPIU)
          1. 5.9.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  DSP Subsystem
    4. 6.4  IPU
    5. 6.5  EVE
    6. 6.6  Memory Subsystem
      1. 6.6.1 EMIF
      2. 6.6.2 GPMC
      3. 6.6.3 ELM
      4. 6.6.4 OCMC
    7. 6.7  Interprocessor Communication
      1. 6.7.1 Mailbox
      2. 6.7.2 Spinlock
    8. 6.8  Interrupt Controller
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  VIP
      2. 6.10.2  DSS
      3. 6.10.3  ADC
      4. 6.10.4  ISS
      5. 6.10.5  Timers
        1. 6.10.5.1 General-Purpose Timers
        2. 6.10.5.2 32-kHz Synchronized Timer (COUNTER_32K)
      6. 6.10.6  I2C
      7. 6.10.7  UART
        1. 6.10.7.1 UART Features
      8. 6.10.8  McSPI
      9. 6.10.9  QSPI
      10. 6.10.10 McASP
      11. 6.10.11 DCAN
      12. 6.10.12 MCAN
      13. 6.10.13 GMAC_SW
      14. 6.10.14 SDIO
      15. 6.10.15 GPIO
      16. 6.10.16 ePWM
      17. 6.10.17 eCAP
      18. 6.10.18 eQEP
    11. 6.11 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1  Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2  Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3  Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_dspeve Example Analysis
    4. 7.4  Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
        1. 7.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):
        2. 7.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):
    5. 7.5  Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 CSI2 Board Design and Routing Guidelines
        1. 7.5.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.2.1.1 General Guidelines
          2. 7.5.2.1.2 Length Mismatch Guidelines
            1. 7.5.2.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.2.1.3 Frequency-domain Specification Guidelines
    6. 7.6  Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7  LPDDR2 Board Design and Layout Guidelines
      1. 7.7.1 LPDDR2 Board Designs
      2. 7.7.2 LPDDR2 Device Configurations
      3. 7.7.3 LPDDR2 Interface
        1. 7.7.3.1 LPDDR2 Interface Schematic
        2. 7.7.3.2 Compatible JEDEC LPDDR2 Devices
        3. 7.7.3.3 LPDDR2 PCB Stackup
        4. 7.7.3.4 LPDDR2 Placement
        5. 7.7.3.5 LPDDR2 Keepout Region
        6. 7.7.3.6 LPDDR2 Net Classes
        7. 7.7.3.7 LPDDR2 Signal Termination
        8. 7.7.3.8 LPDDR2 DDR_VREF Routing
      4. 7.7.4 Routing Specification
        1. 7.7.4.1 DQS[x] and DQ[x] Routing Specification
        2. 7.7.4.2 CK and ADDR_CTRL Routing Specification
    8. 7.8  DDR2 Board Design and Layout Guidelines
      1. 7.8.1 DDR2 General Board Layout Guidelines
      2. 7.8.2 DDR2 Board Design and Layout Guidelines
        1. 7.8.2.1 Board Designs
        2. 7.8.2.2 DDR2 Interface
          1. 7.8.2.2.1  DDR2 Interface Schematic
          2. 7.8.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.8.2.2.3  PCB Stackup
          4. 7.8.2.2.4  Placement
          5. 7.8.2.2.5  DDR2 Keepout Region
          6. 7.8.2.2.6  Bulk Bypass Capacitors
          7. 7.8.2.2.7  High-Speed Bypass Capacitors
          8. 7.8.2.2.8  Net Classes
          9. 7.8.2.2.9  DDR2 Signal Termination
          10. 7.8.2.2.10 VREF Routing
        3. 7.8.2.3 DDR2 CK and ADDR_CTRL Routing
    9. 7.9  DDR3 Board Design and Layout Guidelines
      1. 7.9.1 DDR3 General Board Layout Guidelines
      2. 7.9.2 DDR3 Board Design and Layout Guidelines
        1. 7.9.2.1  Board Designs
        2. 7.9.2.2  DDR3 Device Combinations
        3. 7.9.2.3  DDR3 Interface Schematic
          1. 7.9.2.3.1 32-Bit DDR3 Interface
          2. 7.9.2.3.2 16-Bit DDR3 Interface
        4. 7.9.2.4  Compatible JEDEC DDR3 Devices
        5. 7.9.2.5  PCB Stackup
        6. 7.9.2.6  Placement
        7. 7.9.2.7  DDR3 Keepout Region
        8. 7.9.2.8  Bulk Bypass Capacitors
        9. 7.9.2.9  High-Speed Bypass Capacitors
          1. 7.9.2.9.1 Return Current Bypass Capacitors
        10. 7.9.2.10 Net Classes
        11. 7.9.2.11 DDR3 Signal Termination
        12. 7.9.2.12 VTT
        13. 7.9.2.13 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.9.2.13.1 Three DDR3 Devices
            1. 7.9.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices
            2. 7.9.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices
          2. 7.9.2.13.2 Two DDR3 Devices
            1. 7.9.2.13.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.9.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.9.2.13.3 One DDR3 Device
            1. 7.9.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.9.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        14. 7.9.2.14 Data Topologies and Routing Definition
          1. 7.9.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.9.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        15. 7.9.2.15 Routing Specification
          1. 7.9.2.15.1 CK and ADDR_CTRL Routing Specification
          2. 7.9.2.15.2 DQS and DQ Routing Specification
    10. 7.10 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Community Resources
    6. 8.6 Trademarks
      1. 8.6.1 Electrostatic Discharge Caution
    7. 8.7 Export Control Notice
    8. 8.8 Glossary
  9. 9Mechanical Packaging Information
    1. 9.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.4 Pin Multiplexing

Table 4-28 describes the device pin multiplexing (no characteristics are provided in this table).

NOTE

Table 4-28, Pin Multiplexing doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.3, Signal Descriptions.

NOTE

For more information, see the Control Module / Control Module Functional Description / Pad Configuration Registers section of the Device TRM.

NOTE

Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (Hi-Z mode is not an input signal).

NOTE

When a pad is set into a pin multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

NOTE

In some cases Table 4-28 may present more than one signal per muxmode for the same ball. First signal in the list is the dominant function as selected via CTRL_CORE_PAD_* register.

All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

CAUTION

The IO timings provided in Section 5.9, Timing Requirements and Switching Characteristics are only valid if signals within a single IOSET are used. The IOSETs are defined in the corresponding tables.

Table 4-28 Pin Multiplexing(1)

ADDRESS REGISTER NAME BALL NUMBER MUXMODE[15:0] SETTINGS
0 1 2 3 4 5 6 7 8 9 10 11 12 14 15
E22 xi_osc0
N2 ddr1_a7
AB4 ddr1_d4
W1 ddr1_dqs2
U3 ddr1_d20
C1 ddr1_a1
M19 adc_in0
U1 ddr1_a9
Y6 ddr1_d7
A15 csi2_0_dx3
V1 ddr1_a15
AA2 ddr1_d17
T1 ddr1_a8
R3 ddr1_a11
AA3 ddr1_d16
Y1 ddr1_d23
Y17 ddr1_d14
AA20 ddr1_dqs1
AA6 ddr1_d0
F3 ddr1_cke0
Y20 ddr1_dqsn1
N21 adc_in5
T2 ddr1_a6
W2 ddr1_dqsn2
E3 ddr1_wen
P18 adc_in7
AA11 ddr1_ecc_d2
B3 ddr1_ba0
T17 cvideo_tvout
W22 ddr1_d30
B21 xi_osc1
V3 ddr1_d21
T20 ddr1_d25
A11 csi2_0_dx0
G2 ddr1_nck
U21 ddr1_d24
Y9 ddr1_ecc_d3
R21 ddr1_d26
U4 ddr1_a0
AB18 ddr1_d15
A3 ddr1_ba1
D2 ddr1_ba2
B15 csi2_0_dy3
AA21 ddr1_d10
AA8 ddr1_d1
B13 csi2_0_dy2
AB8 ddr1_dqm0
M22 adc_in3
D1 ddr1_a10
Y3 ddr1_d18
C21 xo_osc1
M20 adc_in1
R22 ddr1_d28
AA9 ddr1_ecc_d6
N3 ddr1_a5
P2 ddr1_odt0
T4 ddr1_a4
AB10 ddr1_dqsn_ecc
AB3 ddr1_dqm2
AA12 ddr1_ecc_d1
AA4 ddr1_d6
T18 cvideo_rset
N22 adc_in4
R4 ddr1_a3
V20 ddr1_d29
AB13 ddr1_dqm_ecc
AA5 ddr1_dqs0
A16 csi2_0_dx4
R2 ddr1_a14
Y2 ddr1_d22
Y21 ddr1_d9
W21 ddr1_dqm3
P20 adc_vrefp
Y5 ddr1_d5
F2 ddr1_casn
AB20 ddr1_d13
B11 csi2_0_dy0
AB9 ddr1_ecc_d7
D22 xo_osc0
U2 ddr1_a12
P19 adc_in6
AA18 ddr1_d8
U22 ddr1_d31
Y18 ddr1_dqm1
A13 csi2_0_dx2
T22 ddr1_dqsn3
G1 ddr1_ck
P17 cvideo_vfb
G3 porz
T21 ddr1_dqs3
Y22 ddr1_d11
AA19 ddr1_d12
AB5 ddr1_dqsn0
U20 ddr1_d27
AA13 ddr1_ecc_d4
B16 csi2_0_dy4
F1 ddr1_rasn
D3 ddr1_a2
AA10 ddr1_dqs_ecc
AA7 ddr1_d3
B2 ddr1_csn0
N1 ddr1_rst
V2 ddr1_d19
Y8 ddr1_d2
B12 csi2_0_dy1
C3 ddr1_a13
A12 csi2_0_dx1
AB11 ddr1_ecc_d5
M21 adc_in2
Y11 ddr1_ecc_d0
0x1400 CTRL_CORE_PAD_GPMC_CLK C12 gpmc_clk rgmii1_txc clkout0 dma_evt1 gpio1_0 Driver off
0x1404 CTRL_CORE_PAD_GPMC_BEN0 D12 gpmc_ben0 rgmii1_txctl ehrpwm1A dma_evt2 gpio1_1 Driver off
0x1408 CTRL_CORE_PAD_GPMC_BEN1 E12 gpmc_ben1 rgmii1_txd3 ehrpwm1B dma_evt3 gpio1_2 Driver off
0x140C CTRL_CORE_PAD_GPMC_ADVN_ALE F12 gpmc_advn_ale rgmii1_txd2 ehrpwm1_tripzone_input clkout1 dma_evt4 gpio1_3 Driver off
0x1410 CTRL_CORE_PAD_GPMC_OEN_REN A10 gpmc_oen_ren rgmii1_txd1 ehrpwm1_synci clkout2 gpio1_4 Driver off
0x1414 CTRL_CORE_PAD_GPMC_WEN B10 gpmc_wen rgmii1_txd0 ehrpwm1_synco gpio1_5 Driver off
0x1418 CTRL_CORE_PAD_GPMC_CS0 C10 gpmc_cs0 rgmii1_rxctl gpio1_6 Driver off
0x141C CTRL_CORE_PAD_GPMC_CS1 E10 gpmc_cs1 qspi1_cs0 gpio1_7 Driver off
0x1420 CTRL_CORE_PAD_GPMC_CS2 D10 gpmc_cs2 qspi1_d3 gpio1_8 Driver off
0x1424 CTRL_CORE_PAD_GPMC_CS3 A9 gpmc_cs3 qspi1_d2 gpio1_9 Driver off
0x1428 CTRL_CORE_PAD_GPMC_CS4 B9 gpmc_cs4 qspi1_d0 gpio1_10 Driver off
0x142C CTRL_CORE_PAD_GPMC_CS5 F10 gpmc_cs5 qspi1_d1 gpio1_11 Driver off
0x1430 CTRL_CORE_PAD_GPMC_CS6 C8 gpmc_cs6 qspi1_sclk gpio1_12 Driver off
0x1434 CTRL_CORE_PAD_GPMC_WAIT0 D8 gpmc_wait0 rgmii1_rxd3 qspi1_rtclk dma_evt4 gpio1_13 Driver off
0x1438 CTRL_CORE_PAD_GPMC_AD0 E8 gpmc_ad0 rgmii1_rxd2 gpio1_14 sysboot0
0x143C CTRL_CORE_PAD_GPMC_AD1 A7 gpmc_ad1 rgmii1_rxd1 gpio1_15 sysboot1
0x1440 CTRL_CORE_PAD_GPMC_AD2 F8 gpmc_ad2 rgmii1_rxd0 gpio1_16 sysboot2
0x1444 CTRL_CORE_PAD_GPMC_AD3 B7 gpmc_ad3 qspi1_rtclk gpio1_17 sysboot3
0x1448 CTRL_CORE_PAD_GPMC_AD4 A6 gpmc_ad4 cam_strobe gpio1_18 sysboot4
0x144C CTRL_CORE_PAD_GPMC_AD5 F7 gpmc_ad5 uart2_txd timer6 spi3_d1 gpio1_19 sysboot5 mcasp2_aclkx
0x1450 CTRL_CORE_PAD_GPMC_AD6 E7 gpmc_ad6 uart2_rxd timer5 spi3_d0 gpio1_20 sysboot6 mcasp2_fsx
0x1454 CTRL_CORE_PAD_GPMC_AD7 C6 gpmc_ad7 cam_shutter timer4 spi3_sclk gpio1_21 Driver off mcasp2_ahclkx
0x1458 CTRL_CORE_PAD_GPMC_AD8 B6 gpmc_ad8 timer7 spi3_cs0 gpio1_22 sysboot8 mcasp2_aclkr
0x145C CTRL_CORE_PAD_GPMC_AD9 A5 gpmc_ad9 eCAP1_in_PWM1_out spi3_cs1 gpio1_23 sysboot9 mcasp2_fsr
0x1460 CTRL_CORE_PAD_GPMC_AD10 D6 gpmc_ad10 timer2 gpio1_24 sysboot10 mcasp2_axr0
0x1464 CTRL_CORE_PAD_GPMC_AD11 C5 gpmc_ad11 timer3 gpio1_25 sysboot11 mcasp2_axr1
0x1468 CTRL_CORE_PAD_GPMC_AD12 B5 gpmc_ad12 gpio1_26 sysboot12 mcasp2_axr2
0x146C CTRL_CORE_PAD_GPMC_AD13 D7 gpmc_ad13 rgmii1_rxc gpio1_27 sysboot13 mcasp2_axr3
0x1470 CTRL_CORE_PAD_GPMC_AD14 B4 gpmc_ad14 spi2_cs1 gpio1_28 sysboot14 mcasp2_axr4
0x1474 CTRL_CORE_PAD_GPMC_AD15 A4 gpmc_ad15 spi2_cs0 gpio1_29 sysboot15 mcasp2_axr5
0x1478 CTRL_CORE_PAD_VIN1A_CLK0 F22 vin1a_clk0 cpi_pclk clkout0 gpio1_30 Driver off mcasp3_aclkx
0x147C CTRL_CORE_PAD_VIN1A_DE0 F21 vin1a_de0 cpi_hsync vin1b_clk1 clkout1 gpio1_31 Driver off
0x1480 CTRL_CORE_PAD_VIN1A_FLD0 F20 vin1a_fld0 cpi_vsync vin2b_clk1 clkout2 gpio2_0 Driver off mcasp3_aclkr
0x1484 CTRL_CORE_PAD_VIN1A_HSYNC0 F19 vin1a_hsync0 cpi_data0 vin1a_de0 gpio2_1 Driver off mcasp3_fsr
0x1488 CTRL_CORE_PAD_VIN1A_VSYNC0 G19 vin1a_vsync0 cpi_data1 gpio2_2 Driver off mcasp3_axr0
0x148C CTRL_CORE_PAD_VIN1A_D0 G18 vin1a_d0 cpi_data2 gpio2_3 Driver off mcasp3_axr1
0x1490 CTRL_CORE_PAD_VIN1A_D1 G21 vin1a_d1 cpi_data3 gpio2_4 Driver off mcasp3_axr2
0x1494 CTRL_CORE_PAD_VIN1A_D2 G22 vin1a_d2 cpi_data4 gpio2_5 Driver off mcasp3_axr3
0x1498 CTRL_CORE_PAD_VIN1A_D3 H18 vin1a_d3 cpi_data5 gpio2_6 Driver off mcasp3_axr4
0x149C CTRL_CORE_PAD_VIN1A_D4 H20 vin1a_d4 cpi_data6 gpio2_7 Driver off mcasp3_axr5
0x14A0 CTRL_CORE_PAD_VIN1A_D5 H19 vin1a_d5 cpi_data7 gpio2_8 xref_clk2 mcasp3_ahclkx
0x14A4 CTRL_CORE_PAD_VIN1A_D6 H22 vin1a_d6 cpi_data8 gpio2_9 Driver off mcasp3_fsx
0x14A8 CTRL_CORE_PAD_VIN1A_D7 H21 vin1a_d7 cpi_data9 gpio2_10 Driver off
0x14AC CTRL_CORE_PAD_VIN1A_D8 J17 vin1a_d8 cpi_data10 vin1b_d0 gpmc_a8 sys_nirq2 gpio2_11 Driver off
0x14B0 CTRL_CORE_PAD_VIN1A_D9 K22 vin1a_d9 cpi_data11 vin1b_d1 gpmc_a9 sys_nirq1 gpio2_12 Driver off
0x14B4 CTRL_CORE_PAD_VIN1A_D10 K21 vin1a_d10 cpi_data12 vin1b_d2 gpmc_a10 sys_nirq2 gpio2_13 Driver off
0x14B8 CTRL_CORE_PAD_VIN1A_D11 K18 vin1a_d11 cpi_data13 vin1b_d3 gpmc_a11 sys_nirq1 gpio2_14 Driver off
0x14BC CTRL_CORE_PAD_VIN1A_D12 K17 vin1a_d12 cpi_data14 vin1b_d4 gpmc_a12 dma_evt1 gpio2_15 Driver off
0x14C0 CTRL_CORE_PAD_VIN1A_D13 K19 vin1a_d13 cpi_wen vin1b_d5 gpmc_a13 dma_evt2 gpio2_16 Driver off
0x14C4 CTRL_CORE_PAD_VIN1A_D14 K20 vin1a_d14 cpi_fid vin1b_d6 gpmc_a14 gpio2_17 Driver off
0x14C8 CTRL_CORE_PAD_VIN1A_D15 L21 vin1a_d15 cpi_data15 vin1b_d7 gpmc_a15 gpio2_18 Driver off
0x14CC CTRL_CORE_PAD_VIN2A_CLK0 L22 vin2a_clk0 gpio2_19 Driver off
0x14D0 CTRL_CORE_PAD_VIN2A_DE0 M17 vin2a_de0 cam_strobe vin2b_hsync1 vin2b_de1 gpio4_21 Driver off
0x14D4 CTRL_CORE_PAD_VIN2A_FLD0 M18 vin2a_fld0 cam_shutter vin2b_vsync1 gpio4_22 Driver off
0x14D8 CTRL_CORE_PAD_VOUT1_CLK AB17 vout1_clk vin1a_d12 clkout0 vin2a_clk0 gpio2_20 Driver off
0x14DC CTRL_CORE_PAD_VOUT1_DE U17 vout1_de mcasp1_aclkx vin1a_d13 clkout1 gpio2_21 Driver off
0x14E0 CTRL_CORE_PAD_VOUT1_FLD W17 vout1_fld mcasp1_fsx vin1a_d14 clkout2 gpio2_22 Driver off
0x14E4 CTRL_CORE_PAD_VOUT1_HSYNC AA17 vout1_hsync mcasp1_aclkr vin1a_d15 vin2a_de0 gpio2_23 Driver off
0x14E8 CTRL_CORE_PAD_VOUT1_VSYNC U16 vout1_vsync mcasp1_fsr vin2a_fld0 gpio2_24 Driver off
0x14EC CTRL_CORE_PAD_VOUT1_D0 W16 vout1_d0 mcasp1_axr0 mmc_clk gpio2_25 Driver off
0x14F0 CTRL_CORE_PAD_VOUT1_D1 V16 vout1_d1 mcasp1_axr1 mmc_cmd gpio2_26 Driver off
0x14F4 CTRL_CORE_PAD_VOUT1_D2 U15 vout1_d2 mcasp1_axr2 mcasp1_axr8 mmc_dat0 gpio2_27 Driver off
0x14F8 CTRL_CORE_PAD_VOUT1_D3 V15 vout1_d3 mcasp1_axr3 mcasp1_axr9 mmc_dat1 gpio2_28 Driver off
0x14FC CTRL_CORE_PAD_VOUT1_D4 Y15 vout1_d4 mcasp1_axr4 mcasp1_axr10 mmc_dat2 gpio2_29 Driver off
0x1500 CTRL_CORE_PAD_VOUT1_D5 W15 vout1_d5 mcasp1_axr5 mcasp1_axr11 mmc_dat3 vin2a_clk0 gpio2_30 Driver off
0x1504 CTRL_CORE_PAD_VOUT1_D6 AA15 vout1_d6 mcasp1_axr6 mcasp1_axr12 emu2 vin2a_de0 gpio2_31 Driver off
0x1508 CTRL_CORE_PAD_VOUT1_D7 AB15 vout1_d7 mcasp1_axr7 eCAP1_in_PWM1_out mcasp1_axr13 emu3 vin2a_fld0 gpio3_0 Driver off
0x150C CTRL_CORE_PAD_VOUT1_D8 AA14 vout1_d8 mcasp1_axr8 vin2a_d0 gpmc_a20 emu4 gpio3_1 Driver off
0x1510 CTRL_CORE_PAD_VOUT1_D9 AB14 vout1_d9 mcasp1_axr9 vin2a_d1 gpmc_a21 emu5 gpio3_2 Driver off
0x1514 CTRL_CORE_PAD_VOUT1_D10 U13 vout1_d10 mcasp1_axr10 vin2a_d2 gpmc_a22 emu6 gpio3_3 Driver off
0x1518 CTRL_CORE_PAD_VOUT1_D11 V13 vout1_d11 mcasp1_axr11 vin2a_d3 gpmc_a23 emu7 gpio3_4 Driver off
0x151C CTRL_CORE_PAD_VOUT1_D12 Y13 vout1_d12 mcasp1_axr12 vin2a_d4 gpmc_a24 emu8 gpio3_5 Driver off mcasp2_ahclkx
0x1520 CTRL_CORE_PAD_VOUT1_D13 W13 vout1_d13 mcasp1_axr13 vin2a_d5 gpmc_a25 emu9 gpio3_6 Driver off mcasp2_aclkr
0x1524 CTRL_CORE_PAD_VOUT1_D14 U11 vout1_d14 mcasp1_axr14 vin2a_d6 gpmc_a26 emu10 gpio3_7 Driver off mcasp2_aclkx
0x1528 CTRL_CORE_PAD_VOUT1_D15 V11 vout1_d15 mcasp1_axr15 vin2a_d7 gpmc_a27 emu11 gpio3_8 Driver off mcasp2_fsx
0x152C CTRL_CORE_PAD_VOUT1_D16 U9 vout1_d16 mcasp1_ahclkx vin2a_d8 gpmc_a0 mcasp1_axr8 vin2b_d0 emu12 gpio3_9 Driver off
0x1530 CTRL_CORE_PAD_VOUT1_D17 W11 vout1_d17 vin2a_d9 gpmc_a1 mcasp1_axr9 vin2b_d1 emu13 gpio3_10 Driver off mcasp2_fsr
0x1534 CTRL_CORE_PAD_VOUT1_D18 V9 vout1_d18 vin2a_d10 gpmc_a2 mcasp1_axr10 vin2b_d2 emu14 gpio3_11 Driver off mcasp2_axr0
0x1538 CTRL_CORE_PAD_VOUT1_D19 W9 vout1_d19 vin2a_d11 gpmc_a3 mcasp1_axr11 vin2b_d3 emu15 gpio3_12 Driver off mcasp2_axr1
0x153C CTRL_CORE_PAD_VOUT1_D20 U8 vout1_d20 vin2a_d12 gpmc_a4 mcasp1_axr12 vin2b_d4 emu16 gpio3_13 Driver off mcasp2_axr2
0x1540 CTRL_CORE_PAD_VOUT1_D21 W8 vout1_d21 vin2a_d13 gpmc_a5 mcasp1_axr13 vin2b_d5 emu17 gpio3_14 Driver off mcasp2_axr3
0x1544 CTRL_CORE_PAD_VOUT1_D22 U7 vout1_d22 vin2a_d14 gpmc_a6 mcasp1_axr14 vin2b_d6 emu18 gpio3_15 Driver off mcasp2_axr4
0x1548 CTRL_CORE_PAD_VOUT1_D23 V7 vout1_d23 vin2a_d15 gpmc_a7 mcasp1_axr15 vin2b_d7 emu19 gpio3_16 Driver off mcasp2_axr5
0x154C CTRL_CORE_PAD_MCAN_TX W7 mcan_tx vin2a_de0 vin2a_hsync0 spi1_cs2 uart3_rxd gpmc_wait1 vin1b_hsync1 vin1b_de1 gpio4_11 Driver off
0x1550 CTRL_CORE_PAD_MCAN_RX W6 mcan_rx cam_nreset vin2a_vsync0 spi1_cs3 uart3_txd gpmc_cs7 vin1b_vsync1 gpio4_12 Driver off
0x1554 CTRL_CORE_PAD_MDIO_MCLK B19 mdio_mclk spi4_d1 gpio3_17 Driver off
0x1558 CTRL_CORE_PAD_MDIO_D B17 mdio_d spi4_d0 gpio3_18 Driver off
0x155C CTRL_CORE_PAD_RGMII0_TXC C16 rgmii0_txc cam_strobe spi4_sclk mmc_clk gpio3_19 Driver off
0x1560 CTRL_CORE_PAD_RGMII0_TXCTL C17 rgmii0_txctl cam_shutter spi4_cs0 mmc_cmd gpio3_20 Driver off
0x1564 CTRL_CORE_PAD_RGMII0_TXD3 E16 rgmii0_txd3 mmc_dat0 gpio3_21 Driver off
0x1568 CTRL_CORE_PAD_RGMII0_TXD2 D16 rgmii0_txd2 eCAP1_in_PWM1_out mmc_dat1 gpio3_22 Driver off
0x156C CTRL_CORE_PAD_RGMII0_TXD1 E17 rgmii0_txd1 mmc_dat2 gpio3_23 Driver off
0x1570 CTRL_CORE_PAD_RGMII0_TXD0 F17 rgmii0_txd0 mmc_dat3 gpio3_24 Driver off
0x1574 CTRL_CORE_PAD_RGMII0_RXC B18 rgmii0_rxc cam_strobe mmc_clk gpio3_25 Driver off
0x1578 CTRL_CORE_PAD_RGMII0_RXCTL C18 rgmii0_rxctl cam_shutter mmc_cmd gpio3_26 Driver off
0x157C CTRL_CORE_PAD_RGMII0_RXD3 A19 rgmii0_rxd3 mmc_dat0 gpio3_27 Driver off
0x1580 CTRL_CORE_PAD_RGMII0_RXD2 B20 rgmii0_rxd2 mmc_dat1 gpio3_28 Driver off
0x1584 CTRL_CORE_PAD_RGMII0_RXD1 C20 rgmii0_rxd1 mmc_dat2 gpio3_29 Driver off
0x1588 CTRL_CORE_PAD_RGMII0_RXD0 A20 rgmii0_rxd0 mmc_dat3 gpio3_30 Driver off
0x158C CTRL_CORE_PAD_XREF_CLK0 M1 xref_clk0 clkout0 spi3_cs0 spi2_cs1 spi1_cs0 spi1_cs1 gpio3_31 Driver off
0x1590 CTRL_CORE_PAD_SPI1_SCLK M2 spi1_sclk uart3_rxd gpio4_0 Driver off
0x1594 CTRL_CORE_PAD_SPI1_D1 U6 spi1_d1 uart3_ctsn gpio4_1 Driver off
0x1598 CTRL_CORE_PAD_SPI1_D0 T5 spi1_d0 uart3_rtsn gpio4_2 Driver off
0x159C CTRL_CORE_PAD_SPI1_CS0 R6 spi1_cs0 uart3_txd gpio4_3 Driver off
0x15A0 CTRL_CORE_PAD_SPI1_CS1 R5 spi1_cs1 spi3_cs1 timer6 ehrpwm1_tripzone_input gpio4_4 Driver off
0x15A4 CTRL_CORE_PAD_SPI2_SCLK L1 spi2_sclk uart3_rxd ehrpwm1A timer3 gpio4_5 Driver off
0x15A8 CTRL_CORE_PAD_SPI2_D1 N4 spi2_d1 uart3_ctsn timer5 eCAP1_in_PWM1_out gpio4_6 Driver off
0x15AC CTRL_CORE_PAD_SPI2_D0 R7 spi2_d0 uart3_rtsn timer1 gpio4_7 sysboot7
0x15B0 CTRL_CORE_PAD_SPI2_CS0 L2 spi2_cs0 uart3_txd ehrpwm1B timer4 gpio4_8 Driver off
0x15B8 CTRL_CORE_PAD_DCAN1_RX N6 dcan1_rx gpio4_10 Driver off
0x15C4 CTRL_CORE_PAD_DCAN1_TX N5 dcan1_tx gpio4_9 Driver off
0x15BC CTRL_CORE_PAD_UART1_RXD F13 uart1_rxd spi4_d1 qspi1_rtclk gpmc_a12 mcan_tx gpio4_13 Driver off
0x15C0 CTRL_CORE_PAD_UART1_TXD E14 uart1_txd spi4_d0 gpmc_a13 mcan_rx gpio4_14 Driver off
0x15C4 CTRL_CORE_PAD_UART1_CTSN F14 uart1_ctsn xref_clk1 uart3_rxd gpmc_a16 spi4_sclk spi1_cs2 timer3 ehrpwm1_synci clkout0 vin2a_hsync0 gpmc_a12 gpmc_clk dcan1_tx gpio4_15 Driver off
0x15C8 CTRL_CORE_PAD_UART1_RTSN C14 uart1_rtsn uart3_txd gpmc_a17 spi4_cs0 spi1_cs3 timer4 ehrpwm1_synco qspi1_rtclk vin2a_vsync0 gpmc_a13 dcan1_rx gpio4_16 Driver off
0x15CC CTRL_CORE_PAD_UART2_RXD D14 uart2_rxd spi3_d1 timer1 ehrpwm1A gpmc_clk gpmc_a12 dcan1_tx gpio4_17 Driver off
0x15D0 CTRL_CORE_PAD_UART2_TXD D15 uart2_txd spi3_d0 timer2 ehrpwm1B gpmc_a13 dcan1_rx gpio4_18 Driver off
0x15D4 CTRL_CORE_PAD_UART2_CTSN F15 uart2_ctsn xref_clk1 gpmc_a18 spi3_sclk qspi1_cs1 timer7 vin2a_hsync0 gpmc_clk mcan_tx gpio4_19 Driver off
0x15D8 CTRL_CORE_PAD_UART2_RTSN F16 uart2_rtsn eCAP1_in_PWM1_out gpmc_a19 spi3_cs0 timer8 vin2a_vsync0 mcan_rx gpio4_20 Driver off
0x15DC CTRL_CORE_PAD_I2C1_SDA L4 i2c1_sda
0x15E0 CTRL_CORE_PAD_I2C1_SCL L3 i2c1_scl
0x15E4 CTRL_CORE_PAD_I2C2_SDA L5 i2c2_sda
0x15E8 CTRL_CORE_PAD_I2C2_SCL L6 i2c2_scl
0x15EC CTRL_CORE_PAD_TMS J3 tms
0x15F0 CTRL_CORE_PAD_TDI J1 tdi gpio4_25 Driver off
0x15F4 CTRL_CORE_PAD_TDO J4 tdo gpio4_26 Driver off
0x15F8 CTRL_CORE_PAD_TCLK J2 tclk
0x15FC CTRL_CORE_PAD_TRSTN J5 trstn
0x1600 CTRL_CORE_PAD_RTCK J6 rtck gpio4_27 Driver off
0x1604 CTRL_CORE_PAD_EMU0 H1 emu0 gpio4_28 Driver off
0x1608 CTRL_CORE_PAD_EMU1 H2 emu1 gpio4_29 Driver off
0x160C CTRL_CORE_PAD_RESETN G4 resetn
0x1610 CTRL_CORE_PAD_NMIN G5 nmin
0x1614 CTRL_CORE_PAD_RSTOUTN F4 rstoutn
  1. NA in table stands for Not Applicable.