SNOSAY8F September 2007 – April 2015 DP83640
PRODUCTION DATA.
MIN | MAX | UNIT | |
---|---|---|---|
Supply Voltage (VCC) | –0.5 | 4.2 | V |
DC Input Voltage (VIN) | –0.5 to VCC + 0.5 | V | |
DC Output Voltage (VOUT) | –0.5 to VCC + 0.5 | V | |
Maximum Case Temperature for TA = 85 °C | 95 | °C | |
Maximum Die Temperature (TJ) | 150 | °C | |
Lead Temperature (TL) (Soldering, 10 s) |
260 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge(3) | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±8000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | MAX | UNIT | |
---|---|---|---|
Analog Supply Voltage (VCC) | 3.3 ± 0.3 | V | |
I/O Supply Voltage (VI/O) | 3.3 ± 10% or 2.5 ± 5% |
V | |
Industrial Temperature (TI) | –40 | 85 | °C |
Power Dissipation (PD) with VI/O = 3.3 V | 290 | mW | |
Power Dissipation (PD) with VI/O = 2.5 V | 260 | mW |
THERMAL METRIC(1) | PT | UNIT | |
---|---|---|---|
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 53.3(2) | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 24.7 |
PIN TYPES |
PARAMETER | TEST CONDITIONS |
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VIH | I I/O |
Input High Voltage | 2.0 | V | |||
VIL | I I/O |
Input Low Voltage | VI/O = 3.3 V | 0.8 | V | ||
VI/O = 2.5 V | 0.7 | V | |||||
IIH | I I/O |
Input High Current | VIN = VI/O | 10 | µA | ||
IIL | I I/O |
Input Low Current | VIN = GND | 10 | µA | ||
VOL | O I/O |
Output Low Voltage | IOL = 4 mA | 0.4 | V | ||
VOH | O I/O |
Output High Voltage | IOH = -4 mA | VI/O - 0.5 | V | ||
IOZ | O I/O |
TRI-STATE Output Leakage Current | VOUT = VI/O or GND | –10 | 10 | µA | |
VTPTD_100 | PMD Output Pair | 100M Transmit Voltage | 0.95 | 1 | 1.05 | V | |
VTPTDsym | PMD Output Pair | 100M Transmit Voltage Symmetry | ±2% | ||||
VTPTD_10 | PMD Output Pair | 10M Transmit Voltage | 2.2 | 2.5 | 2.8 | V | |
VFXTD_100 | PMD Output Pair | FX 100M Transmit Voltage | 0.3 | 0.5 | 0.93 | V | |
CIN1 | I | CMOS Input Capacitance | 8 | pF | |||
COUT1 | O | CMOS Output Capacitance | 8 | pF | |||
SDTHon | PMD Input Pair | 100BASE-TX Signal detect turnon threshold | 1000 | mV diff pk-pk | |||
SDTHoff | PMD Input Pair | Signal detect turnoff threshold | 200 | mV diff pk-pk | |||
VTH | PMD Input Pair | 10BASE-T Receive Threshold | 300 | 585 | mV | ||
Idd100 | Supply | 100BASE-TX (Full Duplex) | VCC = 3.3 V, VI/O = 3.3 V, IOUT = 0 mA(1) | 88 | mA | ||
VCC = 3.3 V, VI/O = 2.5 V, IOUT = 0 mA(1) | 84 | mA | |||||
Idd10 | Supply | 10BASE-T (Full Duplex) | VCC = 3.3 V, VI/O = 3.3 V, IOUT = 0 mA(1) | 105 | mA | ||
VCC = 3.3 V, VI/O = 2.5 V, IOUT = 0 mA(1) | 103 | mA | |||||
Idd | Supply | Power Down Mode | CLK_OUT disabled | 10 | mA |
PARAMETER | DESCRIPTION | NOTES | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
POWER-UP TIMING (Refer to Figure 4-1) | ||||||
T2.1.1 | Post Power Up Stabilization time prior to MDC preamble for register accesses(1) | MDIO is pulled high for 32-bit serial management initialization. | 167 | ms | ||
T2.1.2 | Hardware Configuration Latch-in Time from power up(1) | Hardware Configuration Pins are described in Section 3. | 167 | |||
T2.1.3 | Hardware Configuration pins transition to output drivers | 50 | ns | |||
RESET TIMING (Refer to Figure 4-2) | ||||||
T2.2.1 | Post RESET Stabilization time prior to MDC preamble for register accesses | MDIO is pulled high for 32-bit serial management initialization | 3 | µs | ||
T2.2.2 | Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard) | Hardware Configuration Pins are described in Section 3 | 3 | µs | ||
T2.2.3 | Hardware Configuration pins transition to output drivers(2) | 50 | ns | |||
T2.2.4 | RESET pulse width | X1 Clock must be stable for at min. of 1 µs during RESET pulse low time. | 1 | µs | ||
MII SERIAL MANAGEMENT TIMING (Refer to Figure 4-3) | ||||||
T2.3.1 | MDC to MDIO (Output) Delay Time | 0 | 20 | ns | ||
T2.3.2 | MDIO (Input) to MDC Setup Time | 10 | ||||
T2.3.3 | MDIO (Input) to MDC Hold Time | 10 | ||||
T2.3.4 | MDC Frequency | 2.5 | 25 | MHz | ||
100 Mb/s MII TRANSMIT TIMING (Refer to Figure 4-4) | ||||||
T2.4.1 | TX_CLK High/Low Time | 100 Mb/s Normal mode | 16 | 20 | 24 | ns |
T2.4.2 | TXD[3:0], TX_EN Data Setup to TX_CLK | 10 | ||||
T2.4.3 | TXD[3:0], TX_EN Data Hold from TX_CLK | 0 | ||||
100 Mb/s MII RECEIVE TIMING (Refer to Figure 4-5) | ||||||
T2.5.1 | RX_CLK High/Low Time(3) | 100 Mb/s Normal mode | 16 | 20 | 24 | ns |
T2.5.2 | RX_CLK to RXD[3:0], RX_DV, RX_ER Delay | 10 | 30 | |||
100BASE-TX AND 100BASE-FX MII TRANSMIT PACKET LATENCY TIMING (Refer to Figure 4-6) | ||||||
T2.6.1 | TX_CLK to PMD Output Pair Latency(5) | 100BASE-TX and 100BASE-FX modes IEEE 1588 One-Step Operation enabled(4) |
5 9 |
bits | ||
100BASE-TX AND 100BASE-FX MII TRANSMIT PACKET DEASSERTION TIMING (Refer to Figure 4-7) | ||||||
T2.7.1 | TX_CLK to PMD Output Pair Deassertion(6) | 100BASE-TX and 100BASE-FX modes | 5 | bits | ||
100BASE-TX TRANSMIT TIMING (tR/F and Jitter) (Refer to Figure 4-8) | ||||||
T2.8.1 | 100 Mb/s PMD Output Pair tR and tF(8) | 3 | 4 | 5 | ns | |
100 Mb/s tR and tF Mismatch(7) | 500 | ps | ||||
T2.8.2 | 100 Mb/s PMD Output Pair Transmit Jitter | 1.4 | ns | |||
100BASE-TX AND 100BASE-FX MII RECEIVE PACKET LATENCY TIMING (Refer to Figure 4-9) | ||||||
T2.9.1 | Carrier Sense ON Delay(9) | 100BASE-TX mode | 20 | bits(10) | ||
100BASE-FX mode | 10 | |||||
T2.9.2 | Receive Data Latency(11)(12) | 100BASE-TX mode | 24 | |||
100BASE-FX mode | 14 | |||||
100BASE-TX AND 100BASE-FX MII RECEIVE PACKET DEASSERTION TIMING (Refer to Figure 4-10) | ||||||
T2.10.1 | Carrier Sense OFF Delay(13) | 100BASE-TX mode | 24 | bits(14) | ||
100BASE-FX mode | 14 | |||||
10 Mb/s MII TRANSMIT TIMING(15) (Refer to Figure 4-11) | ||||||
T2.11.1 | TX_CLK High/Low Time | 10 Mb/s MII mode | 190 | 200 | 210 | ns |
T2.11.2 | TXD[3:0], TX_EN Data Setup to TX_CLK falling edge | 10 Mb/s MII mode | 25 | |||
T2.11.3 | TXD[3:0], TX_EN Data Hold from TX_CLK rising edge | 10 Mb/s MII mode | 0 | |||
10 Mb/s MII RECEIVE TIMING (Refer to Figure 4-12) | ||||||
T2.12.1 | RX_CLK High/Low Time(16) | 160 | 200 | 240 | ns | |
T2.12.2 | RXD[3:0], RX_DV transition delay from RX_CLK rising edge | 10 Mb/s MII mode | 100 | |||
T2.12.3 | RX_CLK rising edge delay from RXD[3:0], RX_DV valid data | 10 Mb/s MII mode | 100 | |||
10BASE-T MII TRANSMIT TIMING (START OF PACKET) (Refer to Figure 4-13) | ||||||
T2.13.1 | Transmit Output Delay from the | 10 Mb/s MII mode | 3.5 | bits(17) | ||
Falling Edge of TX_CLK | ||||||
10BASE-T MII TRANSMIT TIMING (END OF PACKET) (Refer to Figure 4-14) | ||||||
T2.14.1 | End of Packet High Time | 250 | 300 | ns | ||
(with '0' ending bit) | ||||||
T2.14.2 | End of Packet High Time | 250 | 300 | ns | ||
(with '1' ending bit) | ||||||
10BASE-T MII RECEIVE TIMING (START OF PACKET) (Refer to Figure 4-15) | ||||||
T2.15.1 | Carrier Sense Turnon Delay (PMD Input Pair to CRS) | 630 | 1000 | ns | ||
T2.15.2 | RX_DV Latency(18) | 10 | bits(19) | |||
T2.15.3 | Receive Data Latency | Measurement shown from SFD | 8 | |||
10BASE-T MII RECEIVE TIMING (END OF PACKET) (Refer to Figure 4-16) | ||||||
T2.16.1 | Carrier Sense Turnoff Delay | 1.0 | µs | |||
10 Mb/s HEARTBEAT TIMING (Refer to Figure 4-17) | ||||||
T2.17.1 | CD Heartbeat Delay | All 10 Mb/s modes | 1200 | ns | ||
T2.17.2 | CD Heartbeat Duration | All 10 Mb/s modes | 1000 | |||
10 Mb/s JABBER TIMING (Refer to Figure 4-18) | ||||||
T2.18.1 | Jabber Activation Time | 85 | ms | |||
T2.18.2 | Jabber Deactivation Time | 500 | ||||
10BASE-T NORMAL LINK PULSE TIMING(20) (Refer to Figure 4-19) | ||||||
T2.19.1 | Pulse Width | 100 | ns | |||
T2.19.2 | Pulse Period | 16 | ms | |||
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING(21) (Refer to Figure 4-20) | ||||||
T2.20.1 | Clock, Data Pulse Width | 100 | ns | |||
T2.20.2 | Clock Pulse to Clock Pulse Period | 125 | µs | |||
T2.20.3 | Clock Pulse to Data Pulse Period | Data = 1 | 62 | |||
T2.20.4 | Burst Width | 2 | ms | |||
T2.20.5 | FLP Burst to FLP Burst Period | 16 | ||||
100BASE-TX SIGNAL DETECT TIMING(22) (Refer to Figure 4-21) | ||||||
T2.21.1 | SD Internal Turnon Time | 1 | ms | |||
T2.21.2 | SD Internal Turnoff Time | Default operation Fast link-loss indication enabled(23) |
250 1.3 |
300 | µs µs |
|
100 Mb/s INTERNAL LOOPBACK TIMING (Refer to Figure 4-22) | ||||||
T2.22.1 | TX_EN to RX_DV Loopback(24) | 100 Mb/s internal loopback mode(25) | 240 | ns | ||
10 Mb/s INTERNAL LOOPBACK TIMING (Refer to Figure 4-23) | ||||||
T2.23.1 | TX_EN to RX_DV Loopback | 10 Mb/s internal loopback mode(26) | 2 | µs | ||
RMII TRANSMIT TIMING (SLAVE MODE) (Refer to Figure 4-24) | ||||||
T2.24.1 | X1 Clock Period | 50-MHz Reference Clock | 20 | ns | ||
T2.24.2 | TXD[1:0], TX_EN, Data Setup to X1 rising edge | 4 | ||||
T2.24.3 | TXD[1:0], TX_EN, Data Hold from X1 rising edge | 2 | ||||
T2.24.4 | X1 Clock to PMD Output Pair Latency (100 Mb)(27) | 100BASE-TX or 100BASE-FX | 11 | bits | ||
RMII TRANSMIT TIMING (MASTER MODE) (Refer to Figure 4-25) | ||||||
T2.25.1 | RX_CLK, TX_CLK, CLK_OUT Period | 50-MHz Reference Clock | 20 | ns | ||
T2.25.2 | TXD[1:0], TX_EN Data Setup to RX_CLK, TX_CLK, CLK_OUT rising edge | 4 | ||||
T2.25.3 | TXD[1:0], TX_EN Data Hold from RX_CLK, TX_CLK, CLK_OUT rising edge | 2 | ||||
T2.25.4 | RX_CLK, TX_CLK, CLK_OUT to PMD Output Pair Latency(28) | From RX_CLK rising edge to first bit of symbol | 11 | bits | ||
RMII RECEIVE TIMING (SLAVE MODE)(29) (Refer to Figure 4-26) | ||||||
T2.26.1 | X1 Clock Period | 50-MHz Reference Clock | 20 | ns | ||
T2.26.2 | RXD[1:0], CRS_DV, and RX_ER output delay from X1 rising edge(30) | 2 | 14 | |||
T2.26.3 | CRS ON delay(31) | 100BASE-TX mode | 18.5 | bits | ||
100BASE-FX mode | 9 | |||||
T2.26.4 | CRS OFF delay (32) | 100BASE-TX mode | 27 | |||
100BASE-FX mode | 17 | |||||
T2.26.5 | RXD[1:0] and RX_ER latency(33)(34)(35) | 100BASE-TX mode | 38 | |||
100BASE-FX mode | 27 | |||||
RMII RECEIVE TIMING (MASTER MODE)(36) (Refer to Figure 4-27) | ||||||
T2.27.1 | RX_CLK, TX_CLK, CLK_OUT Clock Period | 50-MHz Reference Clock | 20 | ns | ||
T2.27.2 | RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from RX_CLK, TX_CLK, CLK_OUT rising edge(37) | 2 | 14 | |||
T2.27.3 | CRS ON delay(38) | 100BASE-TX mode | 18.5 | bits | ||
100BASE-FX mode | 9 | |||||
T2.27.4 | CRS OFF delay (39) | 100BASE-TX mode | 27 | |||
100BASE-FX mode | 17 | |||||
T2.27.5 | RXD[1:0] and RX_ER latency (40) | 100BASE-TX mode | 38 | |||
100BASE-FX mode | 27 | |||||
RX_CLK TIMING (RMII MASTER MODE) (Refer to Figure 4-28) | ||||||
T2.28.1 | RX_CLK High Time(41) | 12 | ns | |||
T2.28.2 | RX_CLK Low Time(41) | 8 | ||||
T2.28.3 | RX_CLK Period | 20 | ||||
CLK_OUT TIMING (RMII SLAVE MODE) (Refer to Figure 4-29) | ||||||
T2.29.1 | CLK_OUT High/Low Time | 10 | ns | |||
T2.29.2 | CLK_OUT propagation delay | Relative to X1 | 8 | |||
SINGLE CLOCK MII (SCMII) TRANSMIT TIMING (Refer to Figure 4-30) | ||||||
T2.30.1 | X1 Clock Period | 25-MHz Reference Clock | 40 | ns | ||
T2.30.2 | TXD[3:0], TX_EN Data Setup | To X1 rising edge | 4 | |||
T2.30.3 | TXD[3:0], TX_EN Data Hold | From X1 rising edge | 2 | |||
T2.30.4 | X1 Clock to PMD Output Pair Latency (100 Mb)(42) | 100BASE-TX or 100BASE-FX | 13 | bits | ||
SINGLE CLOCK MII (SCMII) RECEIVE TIMING (Refer to Figure 4-31) | ||||||
T2.31.1 | X1 Clock Period | 25-MHz Reference Clock(44) | 40 | ns | ||
T2.31.2 | RXD[3:0], RX_DV and RX_ER output delay(43) | From X1 rising edge | 2 | 18 | ||
T2.31.3 | CRS ON delay (45) | 100BASE-TX mode | 19 | bits | ||
100BASE-FX mode | 9 | |||||
T2.31.4 | CRS OFF delay (46) | 100BASE-TX mode | 26 | |||
100BASE-FX mode | 16 | |||||
T2.31.5 | RXD[3:0] and RX_ER latency(47) | 100BASE-TX mode | 56 | |||
100BASE-FX mode | 46 | |||||
100 Mb/s X1 TO TX_CLK TIMING (Refer to Figure 4-32) | ||||||
T2.32.1 | X1 to TX_CLK delay(48) | 100 Mb/s Normal mode | 0 | 5 | ns |