SNLS505G
july 2016 – august 2023
DP83822H
,
DP83822HF
,
DP83822I
,
DP83822IF
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements, Power-Up Timing
7.7
Timing Requirements, Power-Up With Unstable XI Clock
7.8
Timing Requirements, Reset Timing
7.9
Timing Requirements, Serial Management Timing
7.10
Timing Requirements, 100 Mbps MII Transmit Timing
7.11
Timing Requirements, 100 Mbps MII Receive Timing
7.12
Timing Requirements, 10 Mbps MII Transmit Timing
7.13
Timing Requirements, 10 Mbps MII Receive Timing
7.14
Timing Requirements, RMII Transmit Timing
7.15
Timing Requirements, RMII Receive Timing
7.16
Timing Requirements, RGMII
7.17
Normal Link Pulse Timing
7.18
Auto-Negotiation Fast Link Pulse (FLP) Timing
7.19
10BASE-Te Jabber Timing
7.20
100BASE-TX Transmit Latency Timing
7.21
100BASE-TX Receive Latency Timing
7.22
Timing Diagrams
7.23
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Energy Efficient Ethernet
8.3.1.1
EEE Overview
8.3.1.2
EEE Negotiation
8.3.2
Wake-on-LAN Packet Detection
8.3.2.1
Magic Packet Structure
8.3.2.2
Magic Packet Example
8.3.2.3
Wake-on-LAN Configuration and Status
8.3.3
Start of Frame Detect for IEEE 1588 Time Stamp
8.3.4
Clock Output
8.4
Device Functional Modes
8.4.1
MAC Interfaces
8.4.1.1
Media Independent Interface (MII)
8.4.1.2
Reduced Media Independent Interface (RMII)
8.4.1.3
Reduced Gigabit Media Independent Interface (RGMII)
8.4.2
Serial Management Interface
8.4.2.1
Extended Register Space Access
8.4.2.2
Write Address Operation
8.4.2.3
Read Address Operation
8.4.2.4
Write (No Post Increment) Operation
8.4.2.5
Read (No Post Increment) Operation
8.4.2.6
Write (Post Increment) Operation
8.4.2.7
Read (Post Increment) Operation
8.4.2.8
Example Write Operation (No Post Increment)
8.4.2.9
Example Read Operation (No Post Increment)
8.4.3
100BASE-TX
8.4.3.1
100BASE-TX Transmitter
8.4.3.1.1
Code-Group Encoding and Injection
8.4.3.1.2
Scrambler
8.4.3.1.3
NRZ to NRZI Encoder
8.4.3.1.4
Binary to MLT-3 Converter
8.4.3.2
100BASE-TX Receiver
8.4.4
100BASE-FX
8.4.4.1
100BASE-FX Transmit
8.4.4.2
100BASE-FX Receive
8.4.5
10BASE-Te
8.4.5.1
Squelch
8.4.5.2
Normal Link Pulse Detection and Generation
8.4.5.3
Jabber
8.4.5.4
Active Link Polarity Detection and Correction
8.4.6
Auto-Negotiation (Speed / Duplex Selection)
8.4.7
Auto-MDIX Resolution
8.4.8
Loopback Modes
8.4.8.1
Near-End Loopback
8.4.8.2
MII Loopback
8.4.8.3
PCS Loopback
8.4.8.4
Digital Loopback
8.4.8.5
Analog Loopback
8.4.8.6
Far-End (Reverse) Loopback
8.4.9
BIST Configurations
8.4.10
Cable Diagnostics
8.4.10.1
TDR
8.4.11
Fast Link Down Functionality
8.5
Programming
8.5.1
Hardware Bootstrap Configurations
8.5.2
LED Configuration
8.5.3
PHY Address Configuration
8.6
Register Maps
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
TPI Network Circuit
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
Fiber Network Circuit
9.2.2.1
Design Requirements
9.2.2.1.1
Clock Requirements
9.2.2.1.1.1
Oscillator
9.2.2.1.1.2
Crystal
9.2.2.2
Detailed Design Procedure
9.2.2.2.1
MII Layout Guidelines
9.2.2.2.2
RMII Layout Guidelines
9.2.2.2.3
RGMII Layout Guidelines
9.2.2.2.4
MDI Layout Guidelines
9.2.2.3
Application Curves
10
Power Supply Recommendations
10.1
Power Supply Characteristics
11
Layout
11.1
Layout Guidelines
11.1.1
Signal Traces
11.1.2
Return Path
11.1.3
Transformer Layout
11.1.3.1
Transformer Recommendations
11.1.4
Metal Pour
11.1.5
PCB Layer Stacking
11.2
Layout Example
12
Device and Documentation Support
12.1
Related Links
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
13.1
Package Option Addendum
13.1.1
Packaging Information
13.1.2
Tape and Reel Information
Package Options
Mechanical Data (Package|Pins)
RHB|32
MPQF130D
Thermal pad, mechanical data (Package|Pins)
RHB|32
QFND331F
Orderable Information
snls505g_oa
snls505g_pm
9.2.2.1
Design Requirements