SNLS505G july   2016  – august 2023 DP83822H , DP83822HF , DP83822I , DP83822IF

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Power-Up Timing
    7. 7.7  Timing Requirements, Power-Up With Unstable XI Clock
    8. 7.8  Timing Requirements, Reset Timing
    9. 7.9  Timing Requirements, Serial Management Timing
    10. 7.10 Timing Requirements, 100 Mbps MII Transmit Timing
    11. 7.11 Timing Requirements, 100 Mbps MII Receive Timing
    12. 7.12 Timing Requirements, 10 Mbps MII Transmit Timing
    13. 7.13 Timing Requirements, 10 Mbps MII Receive Timing
    14. 7.14 Timing Requirements, RMII Transmit Timing
    15. 7.15 Timing Requirements, RMII Receive Timing
    16. 7.16 Timing Requirements, RGMII
    17. 7.17 Normal Link Pulse Timing
    18. 7.18 Auto-Negotiation Fast Link Pulse (FLP) Timing
    19. 7.19 10BASE-Te Jabber Timing
    20. 7.20 100BASE-TX Transmit Latency Timing
    21. 7.21 100BASE-TX Receive Latency Timing
    22. 7.22 Timing Diagrams
    23. 7.23 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Energy Efficient Ethernet
        1. 8.3.1.1 EEE Overview
        2. 8.3.1.2 EEE Negotiation
      2. 8.3.2 Wake-on-LAN Packet Detection
        1. 8.3.2.1 Magic Packet Structure
        2. 8.3.2.2 Magic Packet Example
        3. 8.3.2.3 Wake-on-LAN Configuration and Status
      3. 8.3.3 Start of Frame Detect for IEEE 1588 Time Stamp
      4. 8.3.4 Clock Output
    4. 8.4 Device Functional Modes
      1. 8.4.1  MAC Interfaces
        1. 8.4.1.1 Media Independent Interface (MII)
        2. 8.4.1.2 Reduced Media Independent Interface (RMII)
        3. 8.4.1.3 Reduced Gigabit Media Independent Interface (RGMII)
      2. 8.4.2  Serial Management Interface
        1. 8.4.2.1 Extended Register Space Access
        2. 8.4.2.2 Write Address Operation
        3. 8.4.2.3 Read Address Operation
        4. 8.4.2.4 Write (No Post Increment) Operation
        5. 8.4.2.5 Read (No Post Increment) Operation
        6. 8.4.2.6 Write (Post Increment) Operation
        7. 8.4.2.7 Read (Post Increment) Operation
        8. 8.4.2.8 Example Write Operation (No Post Increment)
        9. 8.4.2.9 Example Read Operation (No Post Increment)
      3. 8.4.3  100BASE-TX
        1. 8.4.3.1 100BASE-TX Transmitter
          1. 8.4.3.1.1 Code-Group Encoding and Injection
          2. 8.4.3.1.2 Scrambler
          3. 8.4.3.1.3 NRZ to NRZI Encoder
          4. 8.4.3.1.4 Binary to MLT-3 Converter
        2. 8.4.3.2 100BASE-TX Receiver
      4. 8.4.4  100BASE-FX
        1. 8.4.4.1 100BASE-FX Transmit
        2. 8.4.4.2 100BASE-FX Receive
      5. 8.4.5  10BASE-Te
        1. 8.4.5.1 Squelch
        2. 8.4.5.2 Normal Link Pulse Detection and Generation
        3. 8.4.5.3 Jabber
        4. 8.4.5.4 Active Link Polarity Detection and Correction
      6. 8.4.6  Auto-Negotiation (Speed / Duplex Selection)
      7. 8.4.7  Auto-MDIX Resolution
      8. 8.4.8  Loopback Modes
        1. 8.4.8.1 Near-End Loopback
        2. 8.4.8.2 MII Loopback
        3. 8.4.8.3 PCS Loopback
        4. 8.4.8.4 Digital Loopback
        5. 8.4.8.5 Analog Loopback
        6. 8.4.8.6 Far-End (Reverse) Loopback
      9. 8.4.9  BIST Configurations
      10. 8.4.10 Cable Diagnostics
        1. 8.4.10.1 TDR
      11. 8.4.11 Fast Link Down Functionality
    5. 8.5 Programming
      1. 8.5.1 Hardware Bootstrap Configurations
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPI Network Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fiber Network Circuit
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Clock Requirements
            1. 9.2.2.1.1.1 Oscillator
            2. 9.2.2.1.1.2 Crystal
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 MII Layout Guidelines
          2. 9.2.2.2.2 RMII Layout Guidelines
          3. 9.2.2.2.3 RGMII Layout Guidelines
          4. 9.2.2.2.4 MDI Layout Guidelines
        3. 9.2.2.3 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Characteristics
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Transformer Layout
        1. 11.1.3.1 Transformer Recommendations
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-1DE96A67-1AC7-422E-8077-5F7FF489E464-low.gifFigure 6-1 RHB Package
32-Pin VQFN
Top View
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
MAC INTERFACE
TX_CLK 2 O, Hi-Z MII Transmit Clock: MII Transmit Clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed. Note that in MII mode, this clock has constant phase referenced to the reference clock. Applications requiring such constant phase may use this feature.
Hi-Z Unused in RMII Mode
I, PD RGMII Transmit Clock: The clock is sourced from the MAC layer to the PHY. When operating at 100-Mbps speed, this clock must be 25-MHz. When operating at 10-Mbps speed, this clock must be 2.5-MHz.
Note : When in reset, TX_CLK is an output pin and low value is driven on it. Only once device is out of reset, TX_CLK is configured as input.
TX_EN / TX_CTRL 3 I, PD Transmit Enable: TX_EN is presented on the rising edge of the TX_CLK. TX_EN indicates the presence of valid data inputs on TX_D[3:0] in MII mode and on TX_D[1:0] in RMII mode. TX_EN is an active high signal.
RGMII Transmit Control: TX_CTRL combines transmit enable and transmit error signals. TX_EN is presented on the rising edge of TX_CLK and TX_ER on the falling edge of TX_CLK.
TX_D0 4 I, PD Transmit Data: In MII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] received from the MAC is synchronous to the rising edge of the reference clock. In RGMII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of TX_CLK.
TX_D1 5
TX_D2 6
TX_D3 7
RX_CLK 25 O MII Receive Clock: MII Receive Clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the received data stream.
Unused in RMII Mode
RGMII Receive Clock:RGMII Receive Clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the receive data stream.
RX_DV / RX_CTRL 26 O, S-PD Receive Data Valid: This pin indicates valid data is present on the RX_D[3:0] for MII mode and on RX_D[1:0] in RMII mode, independent from Carrier Sense.
RGMII Receive Control: RX_CTRL combines receive data valid and receive error signals. RX_DV is presented on the rising edge of RX_CLK and RX_ER on the falling edge of RX_CLK.
RX_ER 28 O, S-PU Receive Error: This pin indicates that an error symbol has been detected within a received packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is not required to be used by the MAC in MII or RMII because the PHY is corrupting data on a receive error.
Unused in RGMII Mode
RX_D0 30 O, S-PD Receive Data: Symbols received on the cable are decoded and presented on these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A nibble RX_D[3:0] is received in MII and RGMII modes. 2-bits RX_D[1:0] is received in RMII Mode. PHY address pins PHY_AD[4:1] are multiplexed with RX_D[3:0], and are pulled-down. PHY_AD[0] (LSB of the address) is multiplexed with COL on pin 29, and is pulled up. If no external pullup or pulldown is present, the default PHY address is 0x01.
RX_D1 31
RX_D2 32
RX_D3 / GPIO3 1
CRS / CRS_DV 27 O, S-PU Carrier Sense: In MII mode this pin is asserted high when the receive or transmit medium is non-idle.
Carrier Sense / Receive Data Valid: In RMII mode, this pin combines the RMII Carrier and Receive Data Valid indications.
Unused in RGMII Mode
COL / GPIO2 29 I/O, S-PU Collision Detect: For Full-Duplex mode, this pin is always LOW. In Half-Duplex mode, this pin is asserted HIGH only when both transmit and receive media are non-idle.
Unused in RMII Mode
SERIAL MANAGEMENT INTERFACE
MDC 20 I Management Data Clock: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz. There is no minimum clock rate.
MDIO 19 I/O Management Data I/O: Bidirectional management data signal that may be sourced by the management station or the PHY. This pin requires a 2.2-kΩ pullup resistor.
INT/PWDN 8 I/O, OD Interrupt / Power Down: Register access is required for this pin to be configured either as power down or as an interrupt. The default function of this pin is power down. When this pin is configured for a power down function, an active low signal on this pin places the device in power-down mode.
When this pin is configured as an interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pullup. Some applications may require an external pullup resistor.
RESET 18 I, PU RESET: This pin is an active low reset input that initializes or re-initializes all the internal registers of the PHY. Asserting this pin low for at least 10 µs will force a reset process to occur.
CLOCK INTERFACE
XI 23 I Crystal / Oscillator Input
MII reference clock: Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only.
RMII reference clock: Reference clock 50-MHz ±100 ppm-tolerance CMOS-level oscillator in RMII Slave mode. Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator in RMII Master mode.
RGMII reference clock:Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only.
XO 22 O Crystal Output: Reference Clock output. XO pin is used for crystal only. This pin should be left floating when a CMOS-level oscillator is connected to XI.
GPIO AND LED INTERFACE
LED_0 17 O, S-PU Function 1 (Default): LINK Indication, LED indicates the status of the link. When the link is good, LED is ON. When the link is down, LED is OFF.
Function 2: ACT Indication, LED indicates transmit and receive activity in addition to the status of the link. The LED is ON when link is good. The LED blinks when the transmitter or receiver is active.
LED_1 / GPIO1 24 I/O, S-PD Function 1 (Default): This pin is tri-state.
Function 2: SPEED Indication, LED indicates the speed of the link. If speed is 100 Mbps, LED is ON. If speed is 10 Mbps, LED is OFF. External Pull resistors are required when LED is connected to this pin.
GPIO1: This pin can be used as a GPIO when using register access.
Signal Detect: This pin acts as Signal Detect in 100BASE-FX mode and shall be connected with Optical Transceiver. Signal Detect high level will be the VDDIO voltage level.
COL / GPIO2 29 I/O, S, PU MII Mode: COL pin can be used to drive an LED when operating in Full-Duplex mode. Register access is required for LED configuration.
RMII Mode: This pin can be used as an LED when using register access.
RGMII Mode:This pin can be used as an LED when using register access.
GPIO2: This pin can be used as a GPIO when using register access.
RX_D3 / GPIO3 1 I/O, S-PD MII Mode: RX_D3 will remain as RX_D3 because it is required for MII mode.
RMII Mode: RX_D3 pin can be configured to drive an LED. Register access is required for LED configuration.
RGMII Mode:RX_D3 will remain as RX_D3 because it is required for RGMII mode.
GPIO3: This pin can be used as a GPIO when using register access.
MEDIA DEPENDENT INTERFACE
TD_M 11 A Differential Transmit Output (PMD): These differential outputs can be automatically configured to either 10BASE-Te, 100BASE-TX, or 100BASE-FX signaling or forced into a specific signaling mode.
TD_P 12
RD_M 9 A Differential Receive Input (PMD): These differential inputs are automatically configured to accept either 10BASE-Te, 100BASE-TX, or 100BASE-FX signaling or forced into a specific signaling mode.
RD_P 10
POWER AND GROUND PINS
VDDIO 21 P I/O Supply: 3.3 V, 2.5 V, or 1.8 V
AVD 14 P Analog Supply: 3.3 V or 1.8 V
GND Ground
Pad		 P Ground
RBIAS 16 I Bias Resistor Connection. A 4.87-kΩ ±1% resistor must be connected from RBIAS to GND.
OTHER PINS
NC 13 NC Leave Floating
NC 15 NC Leave Floating
LED_1 / GPIO1 24 I/O, S-PD This pin can be left floating when not in used. External Pull resistors are required when LED is connected to this pin.
(1) The definitions below define the functionality of the I/O cells for each pin.
  • Type: I - Input
  • Type: O - Output
  • Type: I/O - Input/Output
  • Type OD - Open Drain
  • Type: PD, PU - Internal Pulldown/Pullup
  • Type: S-PU, S-PD - Strapping Pin (All strap pins have weak internal pullups or pulldowns. If the default strap value is needed to be changed then an external 2.2-kΩ resistor should be used)
Table 6-2 IO Pins State During Reset
PIN NAME NO. TYPE PU/PD/HiZ
MDIO 19 I Hi-Z
MDC 20 I PD
INT_N 8 I PU
RESET_N 18 — —
TX_CLK (1) 2 O PD
TX_EN 3 I PD
TX_D3 7 I PD
TX_D2 6 I PD
TX_D1 5 I PD
TX_D0 4 I PD
LED_0 17 Strap PU
LED_1 24 Strap PD
CRS 27 Strap PU
COL 29 Strap PU
RX_ER 28 Strap PU
RX_DV 26 Strap PD
RX_D3 1 Strap PD
RX_D2 32 Strap PD
RX_D1 21 Strap PD
RX_D0 30 Strap PD
RX_CLK 25 O PD
(1) When in reset, TX_CLK is an output pin and low value is driven on it. In RGMII mode, once device is out of reset, Tx_CLK is configured as input.