SNLS505G july   2016  – august 2023 DP83822H , DP83822HF , DP83822I , DP83822IF

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Power-Up Timing
    7. 7.7  Timing Requirements, Power-Up With Unstable XI Clock
    8. 7.8  Timing Requirements, Reset Timing
    9. 7.9  Timing Requirements, Serial Management Timing
    10. 7.10 Timing Requirements, 100 Mbps MII Transmit Timing
    11. 7.11 Timing Requirements, 100 Mbps MII Receive Timing
    12. 7.12 Timing Requirements, 10 Mbps MII Transmit Timing
    13. 7.13 Timing Requirements, 10 Mbps MII Receive Timing
    14. 7.14 Timing Requirements, RMII Transmit Timing
    15. 7.15 Timing Requirements, RMII Receive Timing
    16. 7.16 Timing Requirements, RGMII
    17. 7.17 Normal Link Pulse Timing
    18. 7.18 Auto-Negotiation Fast Link Pulse (FLP) Timing
    19. 7.19 10BASE-Te Jabber Timing
    20. 7.20 100BASE-TX Transmit Latency Timing
    21. 7.21 100BASE-TX Receive Latency Timing
    22. 7.22 Timing Diagrams
    23. 7.23 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Energy Efficient Ethernet
        1. 8.3.1.1 EEE Overview
        2. 8.3.1.2 EEE Negotiation
      2. 8.3.2 Wake-on-LAN Packet Detection
        1. 8.3.2.1 Magic Packet Structure
        2. 8.3.2.2 Magic Packet Example
        3. 8.3.2.3 Wake-on-LAN Configuration and Status
      3. 8.3.3 Start of Frame Detect for IEEE 1588 Time Stamp
      4. 8.3.4 Clock Output
    4. 8.4 Device Functional Modes
      1. 8.4.1  MAC Interfaces
        1. 8.4.1.1 Media Independent Interface (MII)
        2. 8.4.1.2 Reduced Media Independent Interface (RMII)
        3. 8.4.1.3 Reduced Gigabit Media Independent Interface (RGMII)
      2. 8.4.2  Serial Management Interface
        1. 8.4.2.1 Extended Register Space Access
        2. 8.4.2.2 Write Address Operation
        3. 8.4.2.3 Read Address Operation
        4. 8.4.2.4 Write (No Post Increment) Operation
        5. 8.4.2.5 Read (No Post Increment) Operation
        6. 8.4.2.6 Write (Post Increment) Operation
        7. 8.4.2.7 Read (Post Increment) Operation
        8. 8.4.2.8 Example Write Operation (No Post Increment)
        9. 8.4.2.9 Example Read Operation (No Post Increment)
      3. 8.4.3  100BASE-TX
        1. 8.4.3.1 100BASE-TX Transmitter
          1. 8.4.3.1.1 Code-Group Encoding and Injection
          2. 8.4.3.1.2 Scrambler
          3. 8.4.3.1.3 NRZ to NRZI Encoder
          4. 8.4.3.1.4 Binary to MLT-3 Converter
        2. 8.4.3.2 100BASE-TX Receiver
      4. 8.4.4  100BASE-FX
        1. 8.4.4.1 100BASE-FX Transmit
        2. 8.4.4.2 100BASE-FX Receive
      5. 8.4.5  10BASE-Te
        1. 8.4.5.1 Squelch
        2. 8.4.5.2 Normal Link Pulse Detection and Generation
        3. 8.4.5.3 Jabber
        4. 8.4.5.4 Active Link Polarity Detection and Correction
      6. 8.4.6  Auto-Negotiation (Speed / Duplex Selection)
      7. 8.4.7  Auto-MDIX Resolution
      8. 8.4.8  Loopback Modes
        1. 8.4.8.1 Near-End Loopback
        2. 8.4.8.2 MII Loopback
        3. 8.4.8.3 PCS Loopback
        4. 8.4.8.4 Digital Loopback
        5. 8.4.8.5 Analog Loopback
        6. 8.4.8.6 Far-End (Reverse) Loopback
      9. 8.4.9  BIST Configurations
      10. 8.4.10 Cable Diagnostics
        1. 8.4.10.1 TDR
      11. 8.4.11 Fast Link Down Functionality
    5. 8.5 Programming
      1. 8.5.1 Hardware Bootstrap Configurations
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPI Network Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fiber Network Circuit
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Clock Requirements
            1. 9.2.2.1.1.1 Oscillator
            2. 9.2.2.1.1.2 Crystal
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 MII Layout Guidelines
          2. 9.2.2.2.2 RMII Layout Guidelines
          3. 9.2.2.2.3 RGMII Layout Guidelines
          4. 9.2.2.2.4 MDI Layout Guidelines
        3. 9.2.2.3 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Characteristics
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Transformer Layout
        1. 11.1.3.1 Transformer Recommendations
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Serial Management Interface

The Serial Management Interface provides access to the DP83822 internal register space for status information and configuration. The SMI is compatible with IEEE 802.3 clause 22 and clause 45. The implemented register set consists of the registers required by the IEEE 802.3 plus several others to provide additional visibility and controllability of the DP83822.

The SMI includes the management clock (MDC) and the management input/output data pin (MDIO). MDC is sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of 25 MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when the bus is idle.

MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC. MDIO pin requires a pullup resistor (2.2 KΩ), which pulls MDIO high during IDLE and turnaround.

Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used. During power up or hardware reset, the DP83822 latches the PHY_AD[4:0] configuration pins to determine its address.

The management entity must not start an SMI transaction in the first cycle after power up or hardware reset. To maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after reset is deaserted. In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific). The data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device may actively drive the MDIO signal during the first bit of Turnaround. The addressed DP83822 drives the MDIO with a zero for the second bit of turnaround and follows this with the required data.

For write transactions, the station-management entity writes data to the addressed DP83822, thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>.

Table 8-6 SMI Protocol
SMI PROTOCOL<idle><start><op code><device addr><reg addr><turnaround><data><idle>
Read Operation<idle><01><10><AAAAA><RRRRR><Z0><XXXX XXXX XXXX XXXX><idle>
Write Operation<idle><01><01><AAAAA><RRRRR><10><XXXX XXXX XXXX XXXX><idle>