SNLS505G july   2016  – august 2023 DP83822H , DP83822HF , DP83822I , DP83822IF

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Power-Up Timing
    7. 7.7  Timing Requirements, Power-Up With Unstable XI Clock
    8. 7.8  Timing Requirements, Reset Timing
    9. 7.9  Timing Requirements, Serial Management Timing
    10. 7.10 Timing Requirements, 100 Mbps MII Transmit Timing
    11. 7.11 Timing Requirements, 100 Mbps MII Receive Timing
    12. 7.12 Timing Requirements, 10 Mbps MII Transmit Timing
    13. 7.13 Timing Requirements, 10 Mbps MII Receive Timing
    14. 7.14 Timing Requirements, RMII Transmit Timing
    15. 7.15 Timing Requirements, RMII Receive Timing
    16. 7.16 Timing Requirements, RGMII
    17. 7.17 Normal Link Pulse Timing
    18. 7.18 Auto-Negotiation Fast Link Pulse (FLP) Timing
    19. 7.19 10BASE-Te Jabber Timing
    20. 7.20 100BASE-TX Transmit Latency Timing
    21. 7.21 100BASE-TX Receive Latency Timing
    22. 7.22 Timing Diagrams
    23. 7.23 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Energy Efficient Ethernet
        1. 8.3.1.1 EEE Overview
        2. 8.3.1.2 EEE Negotiation
      2. 8.3.2 Wake-on-LAN Packet Detection
        1. 8.3.2.1 Magic Packet Structure
        2. 8.3.2.2 Magic Packet Example
        3. 8.3.2.3 Wake-on-LAN Configuration and Status
      3. 8.3.3 Start of Frame Detect for IEEE 1588 Time Stamp
      4. 8.3.4 Clock Output
    4. 8.4 Device Functional Modes
      1. 8.4.1  MAC Interfaces
        1. 8.4.1.1 Media Independent Interface (MII)
        2. 8.4.1.2 Reduced Media Independent Interface (RMII)
        3. 8.4.1.3 Reduced Gigabit Media Independent Interface (RGMII)
      2. 8.4.2  Serial Management Interface
        1. 8.4.2.1 Extended Register Space Access
        2. 8.4.2.2 Write Address Operation
        3. 8.4.2.3 Read Address Operation
        4. 8.4.2.4 Write (No Post Increment) Operation
        5. 8.4.2.5 Read (No Post Increment) Operation
        6. 8.4.2.6 Write (Post Increment) Operation
        7. 8.4.2.7 Read (Post Increment) Operation
        8. 8.4.2.8 Example Write Operation (No Post Increment)
        9. 8.4.2.9 Example Read Operation (No Post Increment)
      3. 8.4.3  100BASE-TX
        1. 8.4.3.1 100BASE-TX Transmitter
          1. 8.4.3.1.1 Code-Group Encoding and Injection
          2. 8.4.3.1.2 Scrambler
          3. 8.4.3.1.3 NRZ to NRZI Encoder
          4. 8.4.3.1.4 Binary to MLT-3 Converter
        2. 8.4.3.2 100BASE-TX Receiver
      4. 8.4.4  100BASE-FX
        1. 8.4.4.1 100BASE-FX Transmit
        2. 8.4.4.2 100BASE-FX Receive
      5. 8.4.5  10BASE-Te
        1. 8.4.5.1 Squelch
        2. 8.4.5.2 Normal Link Pulse Detection and Generation
        3. 8.4.5.3 Jabber
        4. 8.4.5.4 Active Link Polarity Detection and Correction
      6. 8.4.6  Auto-Negotiation (Speed / Duplex Selection)
      7. 8.4.7  Auto-MDIX Resolution
      8. 8.4.8  Loopback Modes
        1. 8.4.8.1 Near-End Loopback
        2. 8.4.8.2 MII Loopback
        3. 8.4.8.3 PCS Loopback
        4. 8.4.8.4 Digital Loopback
        5. 8.4.8.5 Analog Loopback
        6. 8.4.8.6 Far-End (Reverse) Loopback
      9. 8.4.9  BIST Configurations
      10. 8.4.10 Cable Diagnostics
        1. 8.4.10.1 TDR
      11. 8.4.11 Fast Link Down Functionality
    5. 8.5 Programming
      1. 8.5.1 Hardware Bootstrap Configurations
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPI Network Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fiber Network Circuit
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Clock Requirements
            1. 9.2.2.1.1.1 Oscillator
            2. 9.2.2.1.1.2 Crystal
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 MII Layout Guidelines
          2. 9.2.2.2.2 RMII Layout Guidelines
          3. 9.2.2.2.3 RGMII Layout Guidelines
          4. 9.2.2.2.4 MDI Layout Guidelines
        3. 9.2.2.3 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Characteristics
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Transformer Layout
        1. 11.1.3.1 Transformer Recommendations
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.1 Hardware Bootstrap Configurations

The DP83822 uses the receive path functional pins as bootstrap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hardware reset, through either the RESET pin or bit[15] in the PHY Reset Control Register (PHYRCR, address 0x001F).

The DP83822 bootstrap pins are 4-level, which are described in greater detail below.

Note:

Because bootstrap pins may have alternate functions after reset is de-asserted, they should not be connected directly to VCC or GND. pullup and pulldown resistors are required for proper operation.

Pins: COL, LED_0, CRS and RX_ER have internal pullup resistors. All other pins with bootstraps have internal pulldown resistors. To account for the difference between the internal pullup and pulldown, please reference Table 8-8 and Table 8-9 below for proper implementation.

LED_0 and LED_1 require parallel pullup or pulldown resistors when using the pin in conjunction with an LED and current limiting resistor.

Configuration of the device may be done via 4-level strapping or via serial management interface. A pullup resistor and a pulldown resistor of suggested values should be used to set the voltage ratio of the bootstrap pin input and the supply to select one of the possible modes.

GUID-05836162-D064-41F0-8B4A-2AC7F7E8215F-low.gif Figure 8-10 Bootstrap Circuits
Table 8-8 Recommended 4-Level Strap Resistor Ratios(1)
MODE IDEAL RH (kΩ) IDEAL RL (kΩ)
PULLDOWN PINS (9 kΩ)
1 (Default) OPEN OPEN
2 10 2.49
3 5.76 2.49
4 2.49 OPEN
PULLUP PINS (50 kΩ)
1 OPEN 1.96
2 13 1.96
3 6.2 1.96
4 (Default) OPEN OPEN
(1) Strap resistors with 1% tolerance are recommended.
Table 8-9 4-Level Strap Voltage Ratios(1)
TARGET VOLTAGE MODE 1 MODE 2 MODE 3 MODE 4
Vmax (V) 0.098 x VDDIO 0.181 x VDDIO 0.277 x VDDIO VDDIO
Vtyp (V) 0 0.165 x VDDIO 0.252 x VDDIO VDDIO
Vmin (V) 0 0.148 x VDDIO 0.227 x VDDIO 0.694 x VDDIO
(1) Ensured by production test, characterization or design.

Table 8-10 describes the DP83822 configuration bootstraps:

Table 8-10 4-Level Strap Pins
PIN NAME PIN # DEFAULT STRAP FUNCTION DESCRIPTION
COL 29 [01] MODE FX_EN PHY_AD0 FX_EN:
Enables 100BASE-FX when set to ‘1’
PHY_AD0:
PHY Address bit[0]
1 0 0
2 1 0
3 1 1
4 (Default) 0 1
RX_D0 30 [10] MODE AN_1 PHY_AD1 AN_1:
See Table 8-11 below
PHY_AD1:
PHY Address bit[1]
1 (Default) 1 0
2 0 0
3 0 1
4 1 1
RX_D1 31 [00] MODE EEE_EN PHY_AD2 EEE_EN:
Enables EEE operation when set to '1'
PHY_AD2:
PHY Address bit [2]
1 (Default) 0 0
2 1 0
3 1 1
4 0 1
RX_D2 32 [00] MODE FLD_EN PHY_AD3 FLD_EN:
Enables Fast Link Drop when set to '1'. Energy Detection, Low SNR threshold and RX_ER will be enabled.
PHY_AD3:
PHY Address bit[3]
1 (Default) 0 0
2 1 0
3 1 1
4 0 1
RX_D3 1 [10] MODE AN_EN PHY_AD4 AN_EN:
See Table 8-11 below
PHY_AD4:
PHY Address bit[4]
1 (Default) 1 0
2 0 0
3 0 1
4 1 1
LED_0 17 [X1] MODE RESERVED AN_0 AN_0:
See Table 8-11 below
1 X 0
2 X Do Not Use(1)
3 X Do Not Use(1)
4 (Default) X 1
LED_1 24 [1X] Mode RESERVED No added functionality.
Do not use Mode 2 & 3
1 (Default) 0
2 Do Not Use(1)
3 Do Not Use(1)
4 1
CRS 27 [01] MODE LED_SPEED LED_CFG LED_CFG:
See below
LED_SPEED:
See Table 8-12 below
1 0 0
2 1 0
3 1 1
4 (Default) 0 1
RX_ER 28 [01] MODE RGMII_EN AMDIX_EN
(SD_EN)		 AMDIX_EN:
Enables Auto-MDIX when set to '1'
RGMII_EN:
See Table 8-13 below
SD_EN:
Enables 100BASE-FX Signal Detection on LED_1 when set to '1'. FX_EN strap must be enabled for SD_EN strap to be functional. Signal Detection is Active HIGH, but polarity can be changed using the Fiber General Configuration Register (FIBER GENCFG, address 0x0465).
1 0 0
2 1 0
3 1 1
4 (Default) 0 1
RX_DV 26 [00] MODE XI_50 RMII_EN XI_50:
See Table 8-13 below
RMII_EN:
See Table 8-13 below
1 (Default) 0 0
2 1 0
3 0 1
4 1 1
(1) Makes the phy go into test mode. Should not be used in funtional mode.
Table 8-11 Modes of Operation
FX_EN AN_EN AN_1 AN_0 Description
Force Modes
0 0 0 0 10BASE-Te, Half-Duplex
0 0 0 1 10BASE-Te, Full-Duplex
0 0 1 0 100BASE-TX, Half-Duplex
0 0 1 1 100BASE-TX, Full-Duplex
Advertised Modes
0 1 0 0 10BASE-Te, Half-Duplex
0 1 0 1 10BASE-Te, Half/Full-Duplex
0 1 1 0 10BASE-Te, Half-Duplex
100BASE-TX, Half-Duplex
0 1 1 1 10BASE-Te, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
Fiber Modes
1 X X 0 100BASE-FX, Half Duplex
1 X X 1 100BASE-FX, Full Duplex
Table 8-12 LED Configuration
CRS Strap Mode LED_SPEED LED_CFG[0] LED_0 LED_1
1 0 0 ON for Good Link
BLINK for TX/RX Activity		 LED_1 in Tri-State
2 1 0 ON for Good Link
BLINK for TX/RX Activity		 ON for 100 Mbps SPEED
OFF for 10 Mbps SPEED
3 1 1 ON for Good Link
OFF for No Link		 ON for 100 Mbps SPEED
OFF for 10 Mbps SPEED
4 0 1 ON for Good Link
OFF for No Link		 LED_1 in Tri-State
Table 8-13 MAC Interface Configuration
RGMII_EN RMII_EN XI_50 Description
0 0 0 MII, 25-MHz Reference Clock
0 0 1 Reserved
0 1 0 RMII, 25-MHz Reference Clock
0 1 1 RMII, 50-MHz Reference Clock
1 X 0 RGMII, 25-MHz Reference Clock
1 X 1 Reserved