15 |
RESERVED |
R |
0x0 |
Reserved
|
14 |
BIST_Error_Counter_Mode |
R/W |
0x0 |
BIST Error Counter Mode:
0x0 = Single mode, when BIST Error Counter reaches its max value, PRBS checker stops counting.
0x1 = Continuous mode, when the BIST Error counter reaches its max value, a pulse is generated and the counter starts counting from zero again.
|
13 |
PRBS_Checker_Config |
R/W |
0x0 |
PRBS Checker Config:bit[13:12]
0x0 = PRBS Generator and Checker both are disabled
0x1 = PRBS Generator Enabled, Trasnmit Single Packet with Constant Data as configured in register 0x001C. Checker is disabled
0x2 = PRBS Generation is disabled. PRBS Checker is Enabled
0x3 = PRBS Generator and Checker both enabled. PRBS Generating Continous Packets as configured in register 0x001C
|
12 |
Packet_Generation_Enable |
R/W |
0x0 |
Packet Generation Enable:bit[13:12]
0x0 = PRBS Generator and Checker both are disabled
0x1 = PRBS Generator Enabled, Trasnmit Single Packet with Constant Data as configured in register 0x001C. Checker is disabled
0x2 = PRBS Generation is disabled. PRBS Checker is Enabled
0x3 = PRBS Generator and Checker both enabled. PRBS Generating Continous Packets as configured in register 0x001C
|
11 |
PRBS_Checker_Lock/Sync |
|
0x0 |
PRBS Checker Lock/Sync Indication:
0x0 = PRBS checker is not locked
0x1 = PRBS checker is locked and synced on received bit stream
|
10 |
PRBS_Checker_Sync_Loss |
H |
0x0 |
PRBS Checker Sync Loss Indication:
0x0 = PRBS checker has not lost sync
0x1 = PRBS checker has lost sync
|
9 |
Packet_Generator_Status |
|
0x0 |
Packet Generation Status Indication:
0x0 = Packet Generator is off
0x1 = Packet Generator is active and generating packets
|
8 |
Power_Mode |
|
0x1 |
Sleep Mode Indication:
0x0 = Indicates that the PHY is in active sleep mode
0x1 = Indicates that the PHY is in normal power mode
|
7 |
RESERVED |
R |
0x0 |
Reserved
|
6 |
Transmit_in_MII_Loopback |
R/W |
0x0 |
Transmit Data in MII Loopback Mode (valid only at 100 Mbps)
0x0 = Data is not transmitted to the line in MII loopback
0x1 = Enable transmission of data from the MAC received on the TX pins to the line in parallel to the MII loopback to RX pins. This bit may be set only in MII Loopback mode - setting bit [14] in in BMCR register (0x0000)
|
5 |
RESERVED |
R |
0x0 |
Reserved
|
4-0 |
Loopback_Mode |
R/W |
0x0 |
Loopback Mode Select: The PHY provides several options for loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the DP83825 digital and analog data paths
0x1 = PCS Input Loopback (Use for 10Base-Te only)
0x2 = PCS Output Loopback
0x4 = Digital Loopback ( Use for 100Base-TX Only)
0x8 = Analog Loopback (requires 100Ω termination)
0x10 = Reverse Loopback
|