7.6.91 DSP_100M_STEP_2_Register Register (Offset = 0x4D5) [reset = 0x2F1]
DSP_100M_STEP_2_Register is shown in Table 103.
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Table 103. DSP_100M_STEP_2_Register Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15-10 |
RESERVED |
R |
0x0 |
Reserved
|
9-7 |
cfg_100m_tloop_kp_step_2 |
R/W |
0x5 |
DSP_100M_STEP_2 Register
|
6-4 |
cfg_100m_tloop_kf_step_2 |
R/W |
0x7 |
DSP_100M_STEP_2 Register
|
3-2 |
cfg_100m_mse_step_2 |
R/W |
0x0 |
DSP_100M_STEP_2 Register
|
1 |
cfg_100m_dfe_step_2 |
R/W |
0x0 |
DSP_100M_STEP_2 Register
|
0 |
cfg_100m_fagc_step_2 |
R/W |
0x1 |
DSP_100M_STEP_2 Register
|