15 |
Disable_PLL |
R/W |
0x0 |
Disable PLL: Note: clock circuitry can be disabled only in IEEE power down mode.
0x0 = Normal operation
0x1 = Disable internal clocks circuitry
|
14 |
Power_Save_Mode_Enable |
R/W |
0x0 |
Power Save Mode Enable:
0x0 = Normal operation
0x1 = Enable power save modes
|
13-12 |
Power_Save_Modes |
R/W |
0x0 |
Power Save Mode:
0x0 = Normal operation mode. PHY is fully functional
0x1 = Reserved
0x2 = Active Sleep, Low Power Active Energy Saving mode that shuts down all internal circuitry besides SMI and energy detect functionalities. In this mode the PHY sends NLP every 1.4 seconds to wake up link partner. Automatic power-up is done when link partner is detected.
|
11 |
Scrambler_Bypass |
R/W |
0x0 |
Scrambler Bypass:
0x0 = Scrambler bypass disabled
0x1 = Scrambler bypass enabled
|
10 |
RESERVED |
R |
0x0 |
Reserved
|
9-8 |
Loopback_FIFO_Depth |
R/W |
0x1 |
Far-End Loopback FIFO Depth: This FIFO is used to adjust RX (receive) clock rate to TX clock rate. FIFO depth needs to be set based on expected maximum packet size and clock accuracy. Default value sets to 5 nibbles.
0x0 = 4 nibbles FIFO
0x1 = 5 nibbles FIFO
0x2 = 6 nibbles FIFO
0x3 = 8 nibbles FIFO
|
7-5 |
RESERVED |
R |
0x0 |
Reserved
|
4 |
RESERVED |
R |
0x0 |
Reserved
|
3 |
Interrupt_Polarity |
R/W |
0x1 |
Interrupt Polarity:
0x0 = Steady state (normal operation) is 0 logic and during interrupt is 1 logic
0x1 = Steady state (normal operation) is 1 logic and during interrupt is 0 logic
|
2 |
Test_Interrupt |
R/W |
0x0 |
Test Interrupt: Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be generated as long as this bit remains set.
0x0 = Do not generate interrupt
0x1 = Generate an interrupt
|
1 |
Interrupt_Enable |
R/W |
0x0 |
Interrupt Enable: Enable interrupt dependent on the event enables in the MISR register (0x0012).
0x0 = Disable event based interrupts
0x1 = Enable event based interrupts
|
0 |
Interrupt_Output_Enable |
R/W |
0x0 |
Interrupt Output Enable: Enable active low interrupt events via the INTR/PWERDN pin by configuring the INTR/PWRDN pin as an output.
0x0 = INTR/PWRDN is a Power Down pin
0x1 = INTR/PWRDN is an interrupt output
|