7.6.34 Register_101 Register (Offset = 0x101) [reset = 0x2082]
Register_101 is shown in Table 46.
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Table 46. Register_101 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15-8 |
cfg_energy_lost_th_normal |
R/W |
0x20 |
DSP_ENERGY_THR_VAL register
|
7 |
cfg_dfe_freeze |
R/W |
0x1 |
DSP_FRZ_CTRL_REGISTER
|
6-5 |
RESERVED |
R |
0x0 |
Reserved
|
4 |
cfg_seq_wd_off |
R/W |
0x0 |
WD_TIMER_CTRL Register
|
3-1 |
cfg_ss_bad_mse_tc_sel |
R/W |
0x1 |
DSP_100M_MSE_TIMER VAL
|
0 |
cfg_use_nrg_det_le_only_as_int |
R/W |
0x0 |
DSP_100M_CTRL register
|