SLLSEC6E September 2012 – June 2019 DP83848-EP
PRODUCTION DATA.
BIT | BIT NAME | DEFAULT | DESCRIPTION | ||||||
---|---|---|---|---|---|---|---|---|---|
15 | MDIX_EN | Strap, RW | Auto-MDIX Enable: | ||||||
1 = Enable Auto-neg Auto-MDIX capability | |||||||||
0 = Disable Auto-neg Auto-MDIX capability | |||||||||
The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR register to be set. If Auto-Negotiation is not enabled, Auto-MDIX should be disabled as well. | |||||||||
14 | FORCE_MDIX | 0, RW | Force MDIX: | ||||||
1 = Force MDI pairs to cross | |||||||||
(Receive on TPTD pair, Transmit on TPRD pair) | |||||||||
0 = Normal operation | |||||||||
13 | PAUSE_RX | 0, RO | Pause Receive Negotiated: | ||||||
Indicates that pause receive should be enabled in the MAC. Based on ANAR[11:10] and ANLPAR[11:10] settings. | |||||||||
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology. | |||||||||
12 | PAUSE_TX | 0, RO | Pause Transmit Negotiated: | ||||||
Indicates that pause transmit should be enabled in the MAC. Based on ANAR[11:10] and ANLPAR[11:10] settings. | |||||||||
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology. | |||||||||
11 | BIST_FE | 0, RW/SC | BIST Force Error: | ||||||
1 = Force BIST Error | |||||||||
0 = Normal operation | |||||||||
This bit forces a single error, and is self clearing | |||||||||
10 | PSR_15 | 0, RW | BIST Sequence select: | ||||||
1 = PSR15 selected | |||||||||
0 = PSR9 selected | |||||||||
9 | BIST_STATUS | 0, LL/RO | BIST Test Status: | ||||||
1 = BIST pass | |||||||||
0 = BIST fail. Latched, cleared when BIST is stopped | |||||||||
For a count number of BIST errors, see the BIST Error Count in the CDCTRL1 register. | |||||||||
8 | BIST_START | 0, RW | BIST Start: | ||||||
1 = BIST start | |||||||||
0 = BIST stop | |||||||||
7 | BP_STRETCH | 0, RW | Bypass LED Stretching: | ||||||
This will bypass the LED stretching and the LEDs will reflect the internal value. | |||||||||
1 = Bypass LED stretching | |||||||||
0 = Normal operation | |||||||||
6 | LED_CNFG[1] | 0, RW | LEDs Configuration: | ||||||
5 | LED_CNFG[0] | Strap, RW | LED_CNFG[1] | LED_ CNFG[0] | Mode Description | ||||
Don’t care | 1 | Mode 1 | |||||||
0 | 0 | Mode 2 | |||||||
1 | 0 | Mode 3 | |||||||
In Mode 1, LEDs are configured as follows: | |||||||||
LED_LINK = ON for Good Link, OFF for No Link | |||||||||
LED_SPEED = ON in 100 Mbps, OFF in 10 Mbps | |||||||||
LED_ACT/COL = ON for Activity, OFF for No Activity | |||||||||
In Mode 2, LEDs are configured as follows: | |||||||||
LED_LINK = ON for good Link, BLINK for Activity | |||||||||
LED_SPEED = ON in 100 Mbps, OFF in 10 Mbps | |||||||||
LED_ACT/COL = ON for Collision, OFF for No Collision | |||||||||
Full Duplex, OFF for Half Duplex | |||||||||
In Mode 3, LEDs are configured as follows: | |||||||||
LED_LINK = ON for Good Link, BLINK for Activity | |||||||||
LED_SPEED = ON in 100 Mbps, OFF in 10 Mbps | |||||||||
LED_ACT/COL = ON for Full Duplex, OFF for Half Duplex | |||||||||
4:0 | PHYADDR[4:0] | Strap, RW | PHY Address: PHY address for port |