SLLSEC6E September 2012 – June 2019 DP83848-EP
PRODUCTION DATA.
PARAMETER | DESCRIPTION | NOTES(1) | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
T2.2.1 | Post RESET stabilization time prior to MDC preamble for register accesses | MDIO is pulled high for 32-bit serial management initialization. | 3 | µs | ||
T2.2.2 | Hardware configuration latch-in time from the deassertion of RESET (either soft or hard) | Hardware configuration pins are described in Section 3 and Table 3-8. | 3 | µs | ||
T2.2.3 | Hardware configuration pins transition to output drivers | 50 | ns | |||
T2.2.4 | RESET pulse width | X1 clock must be stable for at min. of 1 µs during RESET pulse low time. | 1 | µs |