The number of applications requiring Ethernet connectivity continues to increase, driving Ethernet-enabled devices into harsher environments.
The DP83848Q-Q1 was designed to meet the challenge of these new applications with an extended temperature performance that goes beyond the typical Industrial temperature range. The DP83848Q-Q1 is a highly reliable, feature rich, robust device which meets IEEE 802.3u standards over an extended temperature range of –40°C to 105°C. This device is ideally suited for harsh environments such as automotive and transportation, wireless remote base stations, and industrial control applications.
The device offers enhanced ESD protection and the choice of an MII or RMII interface for maximum flexibility in MPU selection; all in a 40 pin WQFN package.
The DP83848Q-Q1 extends the leadership position of the PHYTER™ family of devices with a wide operating temperature range. The TI line of PHYTER transceivers builds on decades of Ethernet expertise to offer the high performance and flexibility that allows the end user an easy implementation tailored to meet these application needs.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DP83848Q-Q1 | WQFN (40) | 6.00 mm × 6.00 mm |
Changes from B Revision (April 2013) to C Revision
Changes from A Revision (April 2013) to B Revision
The DP83848Q-Q1 pins are classified into the following interface categories (each interface is described in the sections that follow):
All DP83848Q-Q1 signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin.
NOTE
Strapping pin option. See Section 3.8 for strap definitions.
PIN NO. | PIN NAME |
---|---|
1 | IO_VDD |
2 | TX_CLK |
3 | TX_EN |
4 | TXD_0 |
5 | TXD_1 |
6 | TXD_2 |
7 | TXD_3 |
8 | RESERVED |
9 | RESERVED |
10 | RESERVED |
11 | RD– |
12 | RD+ |
13 | AGND |
14 | TD– |
15 | TD+ |
16 | PFBIN1 |
17 | AGND |
18 | AVDD33 |
19 | PFBOUT |
20 | RBIAS |
21 | CLK_OUT |
22 | LED_LINK/AN0 |
23 | RESET_N |
24 | MDIO |
25 | MDC |
26 | IOVDD33 |
27 | X2 |
28 | X1 |
29 | DGND |
30 | PFBIN2 |
31 | RX_CLK |
32 | RX_DV/MII_MODE |
33 | CRS/CRS_DV/LED_CFG |
34 | RX_ER/MDIX_EN |
35 | COL/PHYAD0 |
36 | RXD_0/PHYAD1 |
37 | RXD_1/PHYAD2 |
38 | RXD_2/PHYAD3 |
39 | RXD_3/PHYAD4 |
40 | IOGND |
DAP | NC or GND(1) |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
MDC | I | 25 | MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. |
MDIO | I/O | 24 | MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor. |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
TX_CLK | O | 2 | MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock. Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. |
TX_EN | I, PD | 3 | MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0]. RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0]. |
TXD_0 TXD_1 TXD_2 TXD_3 |
I I, PD |
4 5 6 7 |
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode). RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50 MHz reference clock. |
RX_CLK | O | 31 | MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode. Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. |
RX_DV | S, O, PD | 32 | MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0]. Mll mode by default with internal pulldown. RMII Synchronous RECEIVE DATA VALID:This signal provide the RMII Receive Data Valid indication independent of Carrier Sense. |
RX_ER | S, O, PU | 34 | MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode. RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is detected, and CRS_DV is asserted in 100 Mb/s mode. This pin is not required to be used by a MAC in either MII or RMII mode, because the Phy is required to corrupt data on a receive error. |
RXD_0 RXD_1 RXD_2 RXD_3 |
S, O, PD | 36 37 38 39 |
MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted. RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz. |
CRS/CRS_DV | S, O, PU | 33 | MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification. |
COL | S, O, PU | 35 | MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes. While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test). In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation. RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision. |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
X1 | I | 28 | CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848Q-Q1 and must be connected to a 25 MHz 0.005% (±50 ppm) clock source. The DP83848Q-Q1 supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only. RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source. |
X2 | O | 27 | CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used. |
CLK_OUT | O | 21 | MII 25 MHz CLOCK OUTPUT: This pin provides a 25 MHz clock output to the system. This allows other devices to use the reference clock without requiring additional clock sources. RMII 50 MHz CLOCK OUTPUT: Tthis pin provides a 50 MHz clock output to the system. For RMII mode, it is not recommended that the system clock out be used as the reference clock to the MAC. See SNLA076 for more details. |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
LED_LINK | S, O, PU | 22 | LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good. |
LINK/ACT LED: In Mode 2, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active. |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
RESET_N | I, PU | 23 | RESET: Active Low input that initializes or re-initializes the DP83848Q-Q1 . Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Section 5.6. All strap options are re-initialized as well. |
The DP83848Q-Q1 uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.
A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option. If the default option is required, then there is no need for external pullup or pulldown resistors. Because these pins may have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION | |
---|---|---|---|---|
PHYAD0 (COL) PHYAD1 (RXD1_0) PHYAD2 (RXD0_1) PHYAD3 (RXD1_2) PHYAD4 (RXD1_3) |
S, O, PU S, O, PD |
35 36 37 38 39 |
PHY ADDRESS [4:0]: The DP83848Q-Q1 provides five PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset. The DP83848Q-Q1 supports PHY Address strapping values 0 (<00000>) through 31 (<11111>).A PHY Adress of 0 puts the part into the Mll isolate Mode. The Mll isolate mode must be selected by strapping Phy Address 0; changing to Address 0 by register write will not put the Phy in the Mll isolate mode. Refer to Section 5.4.4 for additional information. PHYAD0 pin has weak internal pull-up resistor. PHYAD[4:1] pins have weak internal pull-down resistors. |
|
AN_0 (LED_LINK) | S, O, PU | 22 | AN0: This input pin controls the advertised operating mode of the DP83848Q-Q1 according to the following table. The value on this pin is set by connecting the input pin to GND (0) or VCC (1) through 2.2 kΩ resistors. This pin should NEVER be connected directly to GND or VCC.
The value set at this input is latched into the DP83848Q-Q1 at Hardware-Reset. The float/pull-down status of this pin is latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. The default is 1 because the this pin has an internal pull-up. |
|
AN0 | Advertised Mode | |||
0 | 10BASE-T, Half-Duplex, 100BASE-TX, Half-Duplex |
|||
1 | 10BASE-T, Half/Full-Duplex, 100BASE-TX, Half/Full-Duplex |
|||
MII_MODE (RX_DV) | S, O, PD | 32 | MII MODE SELECT: This strapping option determines the operating mode of the MAC Data Interface. Default operation (No pull-ups) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in the RMII mode of operation. Because the pin includes an internal pull-down, the default value is 0. The following table details the configurations: |
|
MII_MODE | MAC Interface Mode | |||
0 | MII Mode | |||
1 | RMII Mode | |||
LED_CFG (CRS/CRS_DV) | S, O, PU | 33 | LED CONFIGURATION: This strapping option determines the mode of operation of the LED pin. Default is Mode 1. Mode 1 and Mode 2 can be controlled via the strap option. All modes are configurable via register access. See Table 5-2 for LED Mode Selection. |
|
MDIX_EN (RX_ER) | S, O, PU | 34 | MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pull-down will disable Auto-MDIX mode. |
SIGNAL NAME | TYPE | PIN NO. | DESCRIPTION |
---|---|---|---|
RBIAS | I | 20 | Bias Resistor Connection: A 4.87 kΩ 1% resistor should be connected from RBIAS to GND. |
PFBOUT | O | 19 | Power Feedback Output: Parallel caps, 10µF (Tantalum preferred) and 0.1µF, should be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See Section 6.2.1.3 for proper placement pin. |
PFBIN1 PFBIN2 |
I | 16 30 |
Power Feedback Input: These pins are fed with power from PFBOUT pin. A small capacitor of 0.1µF should be connected close to each pin. Note: Do not supply power to these pins other than from PFBOUT. |
RESERVED | I/O | 8, 9, 10 | RESERVED: These pins must be left unconnected. |
SIGNAL NAME | PIN NO. | DESCRIPTION |
---|---|---|
IOVDD33 | 1, 26 | I/O 3.3-V Supply |
IOGND | 40 | I/O Ground |
DGND | 29 | Digital Ground |
AVDD33 | 18 | Analog 3.3-V Supply |
AGND | 13, 17 | Analog Ground |
GNDPAD | DAP | No connect or connect to Ground(1) |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage (VCC) | –0.5 | 4.2 | V | |
DC Input Voltage (VIN) | –0.5 | VCC + 0.5 | V | |
DC Output Voltage (VOUT) | –0.5 | VCC + 0.5 | V | |
Maximum Case Temperature for TA = 105°C | 115 | °C | ||
Maximum Die Temperature (TJ) | 150 | °C | ||
Lead Temp. (TL) | (Soldering, 10 sec.) | 260 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1), (RZAP = 1.5k, CZAP = 100 pF) | ±4000 | V |
MIN | MAX | UNIT | |
---|---|---|---|
Supply voltage (VCC) | 3.3 ± 0.3 | V | |
Ambient Temperature (TA) | –40 | 105 | °C |
Power Dissipation (PD) | 267 | mW |
THERMAL METRIC(1) | DP83848Q-Q1 | UNIT | |
---|---|---|---|
RTA (WQFN) | |||
40 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 34.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 21.1 | |
RθJB | Junction-to-board thermal resistance | 40.5 | |
ψJT | Junction-to-top characterization parameter | 0.4 | |
ψJB | Junction-to-board characterization parameter | 10.5 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 5.5 |
PARAMETER | PIN TYPES |
TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VIH | Input High Voltage | I, | Nominal VCC | 2 | V | ||
I/O | |||||||
VIL | Input Low Voltage | I, | 0.8 | V | |||
I/O | |||||||
IIH | Input High Current | I, | VIN = VCC | 10 | µA | ||
I/O | |||||||
IIL | Input Low Current | I, | VIN = GND | 10 | µA | ||
I/O | |||||||
VOL | Output Low | O, | IOL = 4 mA | 0.4 | V | ||
Voltage | I/O | ||||||
VOH | Output High | O, | IOH = –4 mA | VCC - 0.5 | V | ||
Voltage | I/O | ||||||
IOZ | TRI-STATE | I/O, | VOUT = VCC | ±10 | µA | ||
Leakage | O | VOUT = GND | |||||
VTPTD_100 | 100M Transmit Voltage | PMD Output Pair | 0.95 | 1 | 1.05 | V | |
VTPTDsym | 100M Transmit Voltage Symmetry | PMD Output Pair | ±2% | ||||
VTPTD_10 | 10M Transmit Voltage | PMD Output Pair | 2.2 | 2.5 | 2.8 | V | |
CIN1 | CMOS Input | I | 5 | pF | |||
Capacitance | |||||||
COUT1 | CMOS Output | O | 5 | pF | |||
Capacitance | |||||||
SDTHon | 100BASE-TX | PMD Input Pair | 1000 | mV diff pk-pk | |||
Signal detect turn-on threshold | |||||||
SDTHoff | 100BASE-TX | PMD Input Pair | 200 | mV diff pk-pk | |||
Signal detect turn-off threshold | |||||||
VTH1 | 10BASE-T Receive Threshold | PMD Input Pair | 585 | mV | |||
Idd100 | 100BASE-TX | Supply | 81 | mA | |||
(Full Duplex) | |||||||
Idd10 | 10BASE-T | Supply | 92 | mA | |||
(Full Duplex) | |||||||
Idd | Power Down Mode | Supply | CLK_OUT disabled | 14 | mA |
PARAMETER | DESCRIPTION | NOTES | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
POWER UP TIMING (SEE Figure 4-1) | ||||||
T2.1.1 | Post Power Up Stabilization time prior to MDC preamble for register accesses(1) | MDIO is pulled high for 32-bit serial management initialization | 167 | ms | ||
X1 Clock must be stable for a min. of 167ms at power up. | ||||||
T2.1.2 | Hardware Configuration Latch-in Time from power up(1) | Hardware Configuration Pins are described in the Pin Description section. | 167 | ms | ||
X1 Clock must be stable for a min. of 167ms at power up. | ||||||
T2.1.3 | Hardware Configuration pins transition to output drivers | 50 | ns | |||
RESET TIMING (SEE Figure 4-2) | ||||||
T2.2.1 | Post RESET Stabilization time prior to MDC preamble for register accesses | MDIO is pulled high for 32-bit serial management initialization | 3 | µs | ||
T2.2.2 | Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard)(2) | Hardware Configuration Pins are described in Section 3.2 | 3 | µs | ||
T2.2.3 | Hardware Configuration pins transition to output drivers | 50 | ns | |||
T2.2.4 | RESET pulse width | X1 Clock must be stable for at min. of 1us during RESET pulse low time. | 1 | µs | ||
MII SERIAL MANAGEMENT TIMING (SEE Figure 4-3) | ||||||
T2.3.1 | MDC to MDIO (Output) Delay Time | 0 | 30 | ns | ||
T2.3.2 | MDIO (Input) to MDC Setup Time | 10 | ns | |||
T2.3.3 | MDIO (Input) to MDC Hold Time | 10 | ns | |||
T2.3.4 | MDC Frequency | 2.5 | 25 | MHz | ||
100-Mb/s MII TRANSMIT TIMING (SEE Figure 4-4) | ||||||
T2.4.1 | TX_CLK High/Low Time | 100 Mb/s Normal mode | 16 | 20 | 24 | ns |
T2.4.2 | TXD[3:0], TX_EN Data Setup to TX_CLK | 100 Mb/s Normal mode | 10 | ns | ||
T2.4.3 | TXD[3:0], TX_EN Data Hold from TX_CLK | 100 Mb/s Normal mode | 0 | ns | ||
100-Mb/s MII RECEIVE TIMING (SEE Figure 4-5) | ||||||
T2.5.1 | RX_CLK High/Low Time(3) | 100 Mb/s Normal mode | 16 | 20 | 24 | ns |
T2.5.2 | RX_CLK to RXD[3:0], RX_DV, RX_ER Delay | 100 Mb/s Normal mode | 10 | 30 | ns | |
100BASE-TX MII TRANSMIT PACKET LATENCY TIMING (SEE Figure 4-6) | ||||||
T2.6.1 | TX_CLK to PMD Output Pair Latency(4) | 100BASE-TX modes | bits | |||
100BASE-TX TRANSMIT PACKET DEASSERTION TIMING (SEE Figure 4-7) | ||||||
T2.7.1 | TX_CLK to PMD Output Pair Deassertion(5) | 100BASE-TX mode | 5 | bits | ||
100BASE-TX TRANSMIT TIMING (tR/F AND JITTER) (SEE Figure 4-8) | ||||||
T2.8.1 | 100 Mb/s PMD Output Pair tR and tF | 3 | 4 | 5 | ns | |
100 Mb/s tR and tF Mismatch(6)(7) | 500 | ps | ||||
T2.8.2 | 100 Mb/s PMD Output Pair Transmit Jitter | 1.4 | ns | |||
100BASE-TX RECEIVE PACKET LATENCY TIMING (SEE Figure 4-9) | ||||||
T2.9.1 | Carrier Sense ON Delay(8)(9)(10) | 100 Mb/s Normal mode | 20 | bits | ||
T2.9.2 | Receive Data Latency(9) | 100 Mb/s Normal mode | 24 | bits | ||
100BASE-TX RECEIVE PACKET DEASSERTION TIMING (SEE Figure 4-10) | ||||||
T2.10.1 | Carrier Sense OFF Delay(11)(12) | 100 Mb/s Normal mode | 24 | bits | ||
10-Mb/s MII TRANSMIT TIMING (SEE Figure 4-11) | ||||||
T2.11.1 | TX_CLK High/Low Time | 10 Mb/s MII mode | 190 | 200 | 210 | ns |
T2.11.2 | TXD[3:0], TX_EN Data Setup to TX_CLK fall(13) | 10 Mb/s MII mode | 25 | ns | ||
T2.11.3 | TXD[3:0], TX_EN Data Hold from TX_CLK rise(13) | 10 Mb/s MII mode | 0 | ns | ||
10-Mb/s MII RECEIVE TIMING (SEE Figure 4-12) | ||||||
T2.12.1 | RX_CLK High/Low Time(14) | 160 | 200 | 240 | ns | |
T2.12.2 | RX_CLK TO RXD[3:0}, RX_DV Delay | 10 Mb/s MII mode | 100 | ns | ||
T2.12.3 | RX_CLK rising edge delay from RXD[3:0], RX_DV Valid | 10 Mb/s MII mode | 100 | ns | ||
10BASE-T TRANSMIT TIMING (START OF PACKET) (SEE Figure 4-13) | ||||||
T2.15.1 | Transmit Output Delay from the Falling Edge of TX_CLK(15) | 10 Mb/s MII mode | 3.5 | bits | ||
10BASE-T TRANSMIT TIMING (END OF PACKET) (SEE Figure 4-14) | ||||||
T2.16.1 | End of Packet High Time (with '0' ending bit) | 250 | 300 | ns | ||
T2.16.2 | End of Packet High Time (with '1' ending bit) | 250 | 300 | ns | ||
10BASE-T RECEIVE TIMING (START OF PACKET) (SEE Figure 4-15) | ||||||
T2.17.1 | Carrier Sense Turn On Delay (PMD Input Pair to CRS) | 630 | 1000 | ns | ||
T2.17.2 | RX_DV Latency(16)(17) | 10 | bits | |||
T2.17.3 | Receive Data Latency(17) | Measurement shown from SFD | 8 | bits | ||
10BASE-T RECEIVE TIMING (END OF PACKET) (SEE Figure 4-16) | ||||||
T2.18.1 | Carrier Sense Turn Off Delay | 1 | µs | |||
10-Mb/s HEARTBEAT TIMING (SEE Figure 4-17) | ||||||
T2.19.1 | CD Heartbeat Delay | 10 Mb/s half-duplex mode | 1200 | ns | ||
T2.19.2 | CD Heartbeat Duration | 10 Mb/s half-duplex mode | 1000 | ns | ||
10-Mb/s JABBER TIMING (SEE Figure 4-18) | ||||||
T2.20.1 | Jabber Activation Time | 85 | ms | |||
T2.20.2 | Jabber Deactivation Time | 500 | ms | |||
10BASE-T NORMAL LINK PULSE TIMING (SEE Figure 4-19) | ||||||
T2.21.1 | Pulse Width | 100 | ns | |||
T2.21.2 | Pulse Period | 16 | ms | |||
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING (SEE Figure 4-20) | ||||||
T2.22.1 | Clock, Data Pulse Width | 100 | ns | |||
T2.22.2 | Clock Pulse to Clock Pulse Period | 125 | µs | |||
T2.22.3 | Clock Pulse to Data Pulse Period | Data = 1 | 62 | µs | ||
T2.22.4 | Burst Width | 2 | ms | |||
T2.22.5 | FLP Burst to FLP Burst Period | 16 | ms | |||
100BASE-TX SIGNAL DETECT TIMING (SEE Figure 4-21) | ||||||
T2.23.1 | SD Internal Turn-on Time | 1 | ms | |||
T2.23.2 | SD Internal Turn-off Time | 350 | µs | |||
100-Mb/s INTERNAL LOOPBACK TIMING (SEE Figure 4-22) | ||||||
T2.24.1 | TX_EN to RX_DV Loopback(19)(18) | 100 Mb/s internal loopback mode | 240 | ns | ||
10-Mb/s INTERNAL LOOPBACK TIMING (SEE Figure 4-23) | ||||||
T2.25.1 | TX_EN to RX_DV Loopback(20) | 10 Mb/s internal loopback mode | 2 | µs | ||
RMII TRANSMIT TIMING (SEE Figure 4-24) | ||||||
T2.26.1 | X1 Clock Period | 50 MHz Reference Clock | 20 | ns | ||
T2.26.2 | TXD[1:0], TX_EN, Data Setup to X1 rising | 4 | ns | |||
T2.26.3 | TXD[1:0], TX_EN, Data Hold from X1 rising | 2 | ns | |||
T2.26.4 | X1 Clock to PMD Output Pair Latency | From X1 Rising edge to first bit of symbol | 17 | bits | ||
RMII RECEIVE TIMING (SEE Figure 4-25) | ||||||
T2.27.1 | X1 Clock Period | 50 MHz Reference Clock | 20 | ns | ||
T2.27.2 | RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising(21)(23) | 2 | 14 | ns | ||
T2.27.3 | CRS ON delay (100Mb) | From JK symbol on PMD Receive Pair to initial assertion of CRS_DV(22) | 18.5 | bits | ||
T2.27.4 | CRS OFF delay (100Mb) | From TR symbol on PMD Receive Pair to initial deassertion of CRS_DV(22) | 27 | bits | ||
T2.27.5 | RXD[1:0] and RX_ER latency (100Mb) | From symbol on Receive Pair. Elasticity buffer set to default value (01) | 38 | bits | ||
ISOLATION TIMING (SEE Figure 4-26) | ||||||
T2.28.1 | From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal mode | 100 | µs | |||
T2.28.2 | From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode | 500 | µs | |||
MHz_OUT TIMING (SEE Figure 4-27) | ||||||
T2.29.1 | 25 MHz_OUT High/Low Time | MII mode | 20 | ns | ||
RMII mode | 10 | ns | ||||
T2.29.2 | 25 MHz_OUT propagation delay | Relative to X1 | 8 | ns | ||
100-Mb/s X1 TO TX_CLK TIMING (SEE Figure 4-28) | ||||||
T2.30.1 | X1 to TX_CLK delay(24) | 100 Mb/s Normal mode | 0 | 5 | ns |