SNLS341C March   2011  – March 2015 DP83848Q-Q1

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1  Pin Layout
    2. 3.2  Package Pin Assignments
    3. 3.3  Serial Management Interface
    4. 3.4  MAC Data Interface
    5. 3.5  Clock Interface
    6. 3.6  LED Interface
    7. 3.7  RESET
    8. 3.8  Strap Options
    9. 3.9  10 Mb/s and 100 Mb/s PMD Interface
    10. 3.10 Special Connections
    11. 3.11 Power Supply Pins
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics: DC
    6. 4.6 Electrical Characteristics: AC
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Auto-Negotiation
        1. 5.3.1.1 Auto-Negotiation Pin Control
        2. 5.3.1.2 Auto-Negotiation Register Control
        3. 5.3.1.3 Auto-Negotiation Parallel Detection
        4. 5.3.1.4 Auto-Negotiation Restart
        5. 5.3.1.5 Enabling Auto-Negotiation via Software
        6. 5.3.1.6 Auto-Negotiation Complete Time
      2. 5.3.2 Auto-MDIX
      3. 5.3.3 LED Interface
        1. 5.3.3.1 LEDs
        2. 5.3.3.2 LED Direct Control
      4. 5.3.4 Internal Loopback
      5. 5.3.5 BIST
      6. 5.3.6 Energy Detect Mode
    4. 5.4 Device Functional Modes
      1. 5.4.1 MII Interface
        1. 5.4.1.1 Nibble-wide MII Data Interface
        2. 5.4.1.2 Collision Detect
        3. 5.4.1.3 Carrier Sense
      2. 5.4.2 Reduced MII Interface
      3. 5.4.3 802.3u MII Serial Management Interface
        1. 5.4.3.1 Serial Management Register Access
        2. 5.4.3.2 Serial Management Access Protocol
        3. 5.4.3.3 Serial Management Preamble Suppression
      4. 5.4.4 PHY Address
        1. 5.4.4.1 MII Isolate Mode
      5. 5.4.5 Half Duplex vs. Full Duplex
      6. 5.4.6 Reset Operation
        1. 5.4.6.1 Hardware Reset
        2. 5.4.6.2 Software Reset
    5. 5.5 Programming
      1. 5.5.1 Architecture
        1. 5.5.1.1 100BASE-TX Transmitter
          1. 5.5.1.1.1 Code-Group Encoding and Injection
          2. 5.5.1.1.2 Scrambler
          3. 5.5.1.1.3 NRZ to NRZI Encoder
          4. 5.5.1.1.4 Binary to MLT-3 Convertor
        2. 5.5.1.2 100BASE-TX Receiver
          1. 5.5.1.2.1  Analog Front End
          2. 5.5.1.2.2  Digital Signal Processor
            1. 5.5.1.2.2.1 Digital Adaptive Equalization and Gain Control
            2. 5.5.1.2.2.2 Base Line Wander Compensation
          3. 5.5.1.2.3  Signal Detect
          4. 5.5.1.2.4  MLT-3 to NRZI Decoder
          5. 5.5.1.2.5  NRZI to NRZ
          6. 5.5.1.2.6  Serial to Parallel
          7. 5.5.1.2.7  Descrambler
          8. 5.5.1.2.8  Code-group Alignment
          9. 5.5.1.2.9  4B/5B Decoder
          10. 5.5.1.2.10 100BASE-TX Link Integrity Monitor
          11. 5.5.1.2.11 Bad SSD Detection
        3. 5.5.1.3 10BASE-T Transceiver Module
          1. 5.5.1.3.1  Operational Modes
            1. 5.5.1.3.1.1 Half Duplex Mode
            2. 5.5.1.3.1.2 Full Duplex Mode
          2. 5.5.1.3.2  Smart Squelch
          3. 5.5.1.3.3  Collision Detection and SQE
          4. 5.5.1.3.4  Carrier Sense
          5. 5.5.1.3.5  Normal Link Pulse Detection and Generation
          6. 5.5.1.3.6  Jabber Function
          7. 5.5.1.3.7  Automatic Link Polarity Detection and Correction
          8. 5.5.1.3.8  Transmit and Receive Filtering
          9. 5.5.1.3.9  Transmitter
          10. 5.5.1.3.10 Receiver
    6. 5.6 Memory
      1. 5.6.1 Register Definition
        1. 5.6.1.1 Basic Mode Control Register (BMCR)
        2. 5.6.1.2 Basic Mode Status Register (BMSR)
        3. 5.6.1.3 PHY Identifier Register #1 (PHYIDR1)
        4. 5.6.1.4 PHY Identifier Register #2 (PHYIDR2)
        5. 5.6.1.5 Auto-Negotiation Advertisement Register (ANAR)
        6. 5.6.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 5.6.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 5.6.1.8 Auto-Negotiate Expansion Register (ANER)
        9. 5.6.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
      2. 5.6.2 Extended Registers
        1. 5.6.2.1  PHY Status Register (PHYSTS)
        2. 5.6.2.2  False Carrier Sense Counter Register (FCSCR)
        3. 5.6.2.3  Receiver Error Counter Register (RECR)
        4. 5.6.2.4  100 Mb/s PCS Configuration and Status Register (PCSR)
        5. 5.6.2.5  RMII and Bypass Register (RBR)
        6. 5.6.2.6  LED Direct Control Register (LEDCR)
        7. 5.6.2.7  PHY Control Register (PHYCR)
        8. 5.6.2.8  10 Base-T Status/Control Register (10BTSCR)
        9. 5.6.2.9  CD Test and BIST Extensions Register (CDCTRL1)
        10. 5.6.2.10 Energy Detect Control (EDCR)
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
        1. 6.2.1.1 TPI Network Circuit
        2. 6.2.1.2 Clock IN (X1) Requirements
        3. 6.2.1.3 Power Feedback Circuit
        4. 6.2.1.4 Magnetics
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 MAC Interface (MII/RMII)
        2. 6.2.2.2 Termination Requirement
        3. 6.2.2.3 Recommended Maximum Trace Length
        4. 6.2.2.4 Calculating Impedance
      3. 6.2.3 Application Curve
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 PCB Layout Considerations
      2. 8.1.2 PCB Layer Stacking
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

6.1 Application Information

The device is a physical layer Ethernet transceiver. Typical operating voltage is 3.3 V with power consumption less than 270 mW. When using the device for Ethernet application, it is necessary to meet certain requirements for normal operation of device. Following typical application and design requirements can be used for selecting appropriate component values for DP83848Q-Q1.

6.2 Typical Application

DP83848Q-Q1 fbd_snls341b.gifFigure 6-1 Typical Application

6.2.1 Design Requirements

The design requirements for DP83848Q-Q1 are:

  • Vin = 3.3 V
  • Vout = Vcc – 0.5 V
  • Clock input = 25 MHz for MII and 50 MHz for RMII

6.2.1.1 TPI Network Circuit

Figure 6-2 shows the recommended circuit for a 10/100 Mb/s twisted-pair interface. To the right is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application.

  •  Pulse H1102
  •  Pulse H2019
  •  Pulse J0011D21
  •  Pulse J0011D21B

DP83848Q-Q1 30152511.pngFigure 6-2 10/100-Mb/s Twisted-Pair Interface

6.2.1.2 Clock IN (X1) Requirements

The DP83848Q-Q1 supports an external CMOS level oscillator source or a crystal resonator device.

Oscillator

If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating.

Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 6-1 and Table 6-2.

Crystal

A 25-MHz, parallel, 20-pF load crystal resonator should be used if a crystal source is desired. Figure 6-4 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of 100 mW and a maximum of 500 µW. If a crystal is specified for a lower drive level, a current limiting resistor should be placed in series between X2 and the crystal.

As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1 and CL2 should be set at 33 pF, and R1 should be set at 0 Ω.

Specification for 25-MHz crystal are listed in Table 6-3.

DP83848Q-Q1 30152512.pngFigure 6-3 Crystal Oscillator Circuit

Table 6-1 25-MHz Oscillator Specification

PARAMETER MIN  TYP  MAX  UNIT   CONDITION 
Frequency 25 MHz
Frequency Tolerance ±50 ppm Operational Temperature
Frequency Stability ±50 ppm 1 year aging
Rise / Fall Time 6 nsec 20% - 80%
Jitter 800(1) psec Short term
Jitter 800(1) psec Long term
Symmetry 40% 60% Duty Cycle
(1) This limit is provided as a guideline for component selection and not specified by production testing. Refer to SNLA091, PHYTER 100 Base-TX Reference Clock Jitter Tolerance, for details on jitter performance.

Table 6-2 50-MHz Oscillator Specification

PARAMETER MIN  TYP  MAX  UNIT   CONDITION 
Frequency 50 MHz
Frequency Tolerance ±50 ppm Operational Temperature
Frequency Stability ±50 ppm Operational Temperature
Rise / Fall Time 6 nsec 20% - 80%
Jitter 800(1) psec Short term
Jitter 800(1) psec Long term
Symmetry 40% 60% Duty Cycle
(1) This limit is provided as a guideline for component selection and not specified by production testing. Refer to SNLA091, PHYTER 100 Base-TX Reference Clock Jitter Tolerance, for details on jitter performance.

Table 6-3 25-MHz Crystal Specification

PARAMETER MIN  TYP  MAX  UNIT   CONDITION 
Frequency 25 MHz
Frequency Tolerance ±50 ppm Operational Temperature
Frequency Stability ±50 ppm 1 year aging
Load Capacitance 25 40 pF

6.2.1.3 Power Feedback Circuit

To ensure correct operation for the DP83848Q-Q1 , parallel caps with values of 10 µF and 0.1 µF should be placed close to pin 23 (PFBOUT) of the device.

Pin 18 (PFBIN1), pin 37 (PFBIN2), pin 23 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31 (PFBOUT), each pin requires a small capacitor (0.1 µF). See Figure 6-4 below for proper connections.

DP83848Q-Q1 30152513.gifFigure 6-4 Power Feedback Connection

6.2.1.4 Magnetics

The magnetics have a large impact on the PHY performance as well. While several components are listed below, others may be compatible following the requirements listed in Table 6-4. It is recommended that the magnetics include both an isolation transformer and an integrated common mode choke to reduce EMI. When doing the layout, do not run signals under the magnetics. This could cause unwanted noise crosstalk. Likewise void the planes under discrete magnetics, this will help prevent common mode noise coupling. To save board space and reduce component count, an RJ-45 with integrated magnetics may be used.

Table 6-4 Magnetics Requirements

PARAMETER TYP UNIT CONDITION
Turn Ratio 1:1 — ±2%
Insertion Loss –1 dB 1 MHz to 100 MHz
Return Loss –16 dB 1 MHz to 30 MHz
–12 dB 30 MHz to 60 MHz
–10 dB 60 MHz to 80 MHz
Differential to Common Rejection Ratio –30 dB 1 MHz to 50 MHz
–20 dB 50 MHz to 150 MHz
Crosstalk –35 dB 30 MHz
–30 dB 60 MHz
Isolation 1500 Vrms HPOT

6.2.2 Detailed Design Procedure

6.2.2.1 MAC Interface (MII/RMII)

The Media Independent Interface (MII) connects the PHYTER component to the Media Access Controller (MAC). The MAC may in fact be a discrete device, integrated into a microprocessor, CPU or FPGA. On the MII signals, the IEEE specification states the bus should be 68 ohm impedance. For space critical designs, the PHYTER family of products also support Reduced MII (RMII). For additional information on this mode of operation, refer to the AN-1405 DP83848 Single 10/100 Mb/s Ethernet Transceiver Reduced Media Independent Interface (RMII) Mode Application Report (SNLA076).

6.2.2.2 Termination Requirement

To reduce digital signal energy, 50-Ω series termination resistors are recommended for all MII output signals (including RXCLK, TXCLK, and RX Data signals).

6.2.2.3 Recommended Maximum Trace Length

Although RMII and MII are synchronous bus architectures, there are a number of factors limiting signal trace lengths. With a longer trace, the signal becomes more attenuated at the destination and thus more susceptible to noise interference. Longer traces also act as antennas, and if run on the surface layer, can increase EMI radiation. If a long trace is running near and adjacent to a noisy signal, the unwanted signals could be coupled in as crosstalk. TI recommends keeping the signal trace lengths as short as possible. Ideally, keep the traces under 6 inches. Trace length matching, to within 2 inches on the MII or RMII bus is also recommended. Significant differences in the trace lengths can cause data timing issues. As with any high-speed data signal, good design practices dictate that impedance should be maintained and stubs should be avoided throughout the entire data path.

6.2.2.4 Calculating Impedance

Equation 1 through Equation 4 can be used to calculate the differential impedance of the board. For microstrip traces, a solid ground plane is needed under the signal traces. The ground plane helps keep the EMI localized and the trace impedance continuous. Because stripline traces are typically sandwiched between the ground/supply planes, they have the advantage of lower EMI radiation and less noise coupling. The trade off of using strip line is lower propagation speed.

Microstrip Impedance - Single-Ended:

Equation 1. DP83848Q-Q1 equation1_snls341.gif
DP83848Q-Q1 MSSingle.pngFigure 6-5 Microstrip Impedance - Single-Ended

Stripline Impedance - Single-Ended:

Equation 2. DP83848Q-Q1 equation2_snls341.gif
DP83848Q-Q1 STSingle.pngFigure 6-6 Stripline Impedance – Single Ended

Microstrip Impedance - Differential:

Equation 3. DP83848Q-Q1 equation3_snls341.gif
DP83848Q-Q1 MSDiff.pngFigure 6-7 Microstrip Impedance - Differential

Stripline Impedance - Differential:

Equation 4. DP83848Q-Q1 equation4_snls341.gif
DP83848Q-Q1 STDiff.pngFigure 6-8 Stripline Impedance - Differential

6.2.3 Application Curve

DP83848Q-Q1 20205006.gifFigure 6-9 Sample 100-Mb/s Waveform (MLT-3)
DP83848Q-Q1 20205007.gifFigure 6-10 Sample 10-Mb/s Waveform